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Clock signalBankSourceFPGA PinNotes
B224_CLK0_P224B2B, J3-62MGTREFCLK0P_224, R8Supplied by the carrier board
B224_CLK0_N224B2B, J3-60MGTREFCLK0N_224, R7Supplied by the carrier board
B224_CLK1_P224U5, CLK4_PMGTREFCLK1P_224, N8On-board Si5345A
B224_CLK1_N224U5, CLK4_NMGTREFCLK1N_224, N7On-board Si5345A
B225_CLK0_P225B2B, J3-67MGTREFCLK0P_225, L8Supplied by the carrier board
B225_CLK0_N225B2B, J2J3-65MGTREFCLK0N_225, L7Supplied by the carrier board
B225_CLK1_P225U5, CLK3_PMGTREFCLK1P_225, J8On-board Si5345A
B225_CLK1_N225U5, CLK3_NMGTREFCLK1N_225, J7On-board Si5345A
B226_CLK0_P226U5, CLK2_PMGTREFCLK0P_226, H10On-board Si5345A
B226_CLK0_N226U5, CLK2_NMGTREFCLK0N_226, H9On-board Si5345A
B226_CLK1_P226B2B, J3-61MGTREFCLK1P_226, F10Supplied by the carrier board
B226_CLK1_N226B2B, J3-59MGTREFCLK1N_226, F9Supplied by the carrier board
B227_CLK0_P227U5, CLK1_PMGTREFCLK0P_227, D10On-board Si5345A
B227_CLK0_N227U5, CLK1_NMGTREFCLK0N_227, D9On-board Si5345A
B227_CLK1_P227B2B, J2-22MGTREFCLK1P_227, B10Supplied by the carrier board
B227_CLK1_N227B2B, J2-24MGTREFCLK1N_227, B9Supplied by the carrier board
B505_CLK0_P505B2B, J2-10PS_MGTREFCLK0P_505, M23Supplied by the carrier board
B505_CLK0_N505B2B, J2-12PS_MGTREFCLK0N_505, M24Supplied by the carrier board
B505_CLK1_P505B2B, J2-16PS_MGTREFCLK1P_505, L25Supplied by the carrier board
B505_CLK1_N505B2B, J2-18PS_MGTREFCLK1N_505, L26Supplied by the carrier board
B505_CLK2_P505U5, CLK5_PPS_MGTREFCLK2P_505, K23On-board Si5345A
B505_CLK2_N505U5, CLK5_NPS_MGTREFCLK2N_505, K24On-board Si5345A
B505_CLK3_P505U5, CLK6_PPS_MGTREFCLK3P_505, H23On-board Si5345A
B505_CLK3_N505U5, CLK6_NPS_MGTREFCLK3N_505, H24On-board Si5345A

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  • typo correction SI5345 I2C address
  • typo B2B Pin of CLK signals

v.20Ali Naseri
  • initial document

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