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The board is equipped with a programmable System Controller CPLD provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family) to control the signals of the configured interfaces. The data stream of the USB2.0 port can be also converted to 8 independent GPIO's or used as FIFO.

Following table describes the possible operation modes of the TE0790 adapter board. The operation modes ared determined by the configuration of the FT2232H, which is done by programing the Configuration EEPROM and the System Controller CPLD:

#FTDI
Channel A		FTDI
Channel B		Pins A to GNotes
1JTAG/SPI (MPSSE)UARTJTAG, UARTJTAG compatible to Xilinx, Lattice and open-source software that uses FTDI MPPSE
2JTAG/SPI (MPSSE)JTAG/SPI (MPSSE)JTAG, JTAGDual JTAG, only Channel A is Xilinx compatible
3UARTUARTUART, UARTDual UART
4I2CUARTI2C, UART 
5MPSSE 8x GPIO 
6 UART8x GPIO 
7UARTUARTnot usedUART to UART loopback
8not usedFast Serial FTDI 4-wire fast serial adapter, custom EEPROM is needed to enable this mode
9CPLD update onlynot useduser definedStandalone Module with CPLD and 8 user programmable I/O

Table 1: Initial delivery state of programmable devices on the module.

MPSSE - FTDI protocol that is used by JTAG and SPI adapters based on FTDI devices.

Key Features

  • Xmod form-factor
    • size: 20 x 25 mm
    • M3 mounting hole
  • FT2232H
    • USB2.0 port High Speed (480 Mbps) and Full Speed (12 Mbps) compatible
    • Entire USB protocol handled on the chip
    • USB2.0 to JTAG, SPI and I²C conversion provided by the IC's Multi-Protocol Synchronous Serial Engine (MPSSE)
    • USB2.0 to UART conversion
    • Channel B UART RX/TX LED's
    • Mini-USB B connector (more rigid then micro-USB)
    • 93C56 EEPROM
  • Lattice XO2-256 CPLD
    • on board programmable using Lattice tools
    • 8 universal I/O pins
    • VCCIO either 3.3V or user supplied (1.8 to 3.3V)
    • RED user LED
    • 12 MHz clock from on-board Oscillator
  • LDO DCDC for optional USB power
  • GREEN Power-on LED
  • User button
  • 4 position DIP switch
    • Choose CPLD program mode
    • FTDI EEPROM disable (not implemented in PCB REV 1)
    • Use VIO same as VCC
    • Use VCC from USB

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Storage device name

Content

Notes

Configuration EEPROM U10variant dependingonly programmed on TE-0790-xx,
not programmed on TE0790-xxL variants.

Table 12: Initial delivery state of programmable devices on the module.

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Signal J2 Pin NameJ2 Pin Name Signal
GND 1*GND
User DefinedCAUser Defined
VIO  VDD 3.3V
User DefinedDBUser Defined
User DefinedFEUser Defined
User DefinedHGUser Defined / Button (Reset_n)

Table 23: Pin header J2 signal assignment. *pin 1 on header J2

The signals of the FTDI FT2232H chip are not directly connected to the pin header J2 but routed to the System Controller CPLD of the adapter board, which controls and by-passes the signals to the pin header J2.

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FTDISignalPull up/down J2 Pin NameJ2 Pin Name Pull up/downSignalFTDI
 GND- 1*-GND 
ADBUS0TCK (output from adapter) CAupUART RXD (input to adapter)BDBUS1
 VIO-  -VDD 3.3V 
ADBUS2TDO (input to adapter)upDB UART TXD (output from adapter)BDBUS0
ADBUS1TDI (output from adapter) FEdownLED 
ADBUS3TMS (output from adapter) HGupButton (Reset_n) 

Table 34: Pin header J2 signal assignment with standard configuration firmware. *pin 1 on header J2


Signal assignment on Standard with RXD-TXD Swapped:

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FTDISignalPull up/down J2 Pin NameJ2 Pin Name Pull up/downSignalFTDI
 GND- 1*-GND 
ADBUS0TCK (output from adapter) CA
UART TXD (output from adapter)BDBUS0
 VIO-  -VDD 3.3V 
ADBUS2TDO (input to adapter)upDB upUART RXD (input to adapter)BDBUS1
ADBUS1TDI (output from adapter) FEdownLED 
ADBUS3TMS (output from adapter) HGupButton (Reset_n) 

Table 45: Pin header J2 signal assignment with standard, but RXD-TXD swapped configuration firmware. *pin 1 on header J2


Signal assignment on TE0790 CPLD - XMOD DIP40:

On DIPFORTy, VIO Pin is connected with VDD 3.3V Pin.  UART RXD is connected to FPGA-Pin L13 and UART TXD to K15. Connect XMOD on the top-side (FPGA side) of the PCB.

FTDISignalPull up/down J2 Pin Name J2 Pin NamePull up/downSignalFTDI
 GND- 1*-GND 
BDBUS1UART RXD (input to adapter)upCA TCK (output from adapter)ADBUS0
 VIO-  -VDD 3.3 V 
BDBUS0UART TXD (output from adapter) DB TMS (output from adapter)ADBUS3
ADBUS1TDI (output from adapter) FEupTDO (input to adapter)ADBUS2
 not used HG CPLD User LED 'ULED' 

Table 56: Pin header J2 signal assignment with DIPFORTy firmware.

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In order to work with Xilinx tools special order must be used, in that case the EEPROM is pre-programmed and serialized and will be recognized by all Xilinx tools (ISE/Impact/Chipscope, Vivado Programmer/SDK..).

Warning

Important notice on TE0790-xx variants:

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

The Configuration EEPROM of TE0790-xxL variants are capable of being programmed with FTDI-Tools.

System Controller CPLD

The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces.

Signals of the serial interfaces like JTAG, SPI and I2C or parallel interfaces are by-passed, forwarded and controlled by the System Controller CPLD.

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S2ONOFFDefaultDescription
1Normal modeModule update modeONUpdate Mode JTAG access to SC CPLD only
2Do not useNormal modeOFFDo not change from default, secure configuration EEPROM
3VIO connected to 3.3VPower VIO from pin header J2OFFSC CPLD I/O-voltage from/to pin header
4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)

Table 67: DIP-switch S2 setting description.

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S2-3S2-43.3V (VCC) Pin 5VIO Pin 6Description
OFFOFF3.3V from baseVIO from base3.3V (pin 5) and VIO (pin 6) sourced from base
OFFON3.3V from USBVIO from baseVIO sourced from base by Pin 6
ONOFF3.3V from base3.3V from baseVIO sourced by Pin 5 and drive Pin 6
ONON3.3V from USB3.3V from USBVIO sourced by USB and drive Pin 6

Table 78: DIP-switch S2 power setting description.

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LED ColorConnected toDescription and Notes
D1Green3.3V3.3V power status LED
D2RedFTDI IC, 'RXLED'UART receive data activity
D3RedFTDI IC, 'TXLED'UART transmit data activity
D4RedSC CPLD, 'ULED'user LED, on standard SC CPLD firmware assigned to pins E and G, in DIPFORTy to G

Table 89: On-board LEDs.

Power and Power-On Sequence

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Power Rail Name

Pin Header J2

Direction

Notes
3.3Vpin 5both possibleuser configurable by DIP-switch S2-3 and S2-4
VIOpin 6both possibleuser configurable by DIP-switch S2-3 and S2-4-switch S2-3 and S2-4
GNDpin 1. pin 2--

Table 10Table 9: Module power rails.

Variants Currently In Production

 Module Variant

Xilinx Vivado/SDK Support

Xilinx devices with 3rd Party ToolsAny other MPSSE based JTAG Tools
TE0790-02YesYesYes
TE0790-02LNoYesYes

Table 1011: Module variants.

Variants with TE-0790-xxL do not include the ID String in EEPROM for direct support from Xilinx Vivado.

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ParameterMinMaxUnitsReference Document

3.3V

-0.34VFTDI FT2232H data sheet
VIO-0.53.75VLattice MachX02 Family data sheet
Voltage on pins A - H-0.53.75VLattice MachX02 Family data sheet
Storage temperature-40100°CLED SML-P11 data sheet

Table 1112: Module absolute maximum ratings.

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ParameterMinMaxUnitsReference Document

3.3V

 2.3753.6VLattice MachX02 Family data sheet
VIO1.143.6VLattice MachX02 Family data sheet
Voltage on pins A - H1.143.6VLattice MachX02 Family data sheet
Operating temperature-4085°CFTDI FT2232H data sheet

Table 1213: Module recommended operating conditions.

Operating Temperature

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Range

Commercial Industrial grade: 0°C -40°C to +70°C85°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°CThe TE0790 USB2.0 adapter board is capable to be operated at industrial grade temperature range.

Physical Dimensions

  • Module size: 24,65mm × 20,02mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard pin headers: 8.5 mm.

  • PCB thickness: 1.75 mm.

  • Highest part on PCB: approx. 8.75 mm. Please download the step model for exact numbers.

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DateRevision

Notes

PCNDocumentation Link
-

01

prototypes--
-02current available revision-TE0790-02

Table 1314: Module hardware revision history.

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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Image Modified

Figure 4: Module hardware revision number.

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd



Ali Naseriinitial document

Table 1415: Document change history.

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