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The Trenz Electronic TE0724 is an industrial-grade SoC module based on Xilinx Zynq-7010, which provides a dual core ARM Cortex A9 and a . It provides a gigabit ethernet transceiver, 1GByte of DDR3L SDRAM, 32 MByte Flash memory as configration and data storage. it includes strong pwerregulators for all needed voltages and a robust high-speed connector for in- and outputs. It has a 6 x 4 cm form factor.

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Additional assembly options are available for cost or performance optimization upon request.

Main Components

Table 1: TE0xxx-xx main components.

Add description list of PCB labels here...

Initial Delivery State

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Storage device name

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Content

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Notes

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Table 1: Initial delivery state of programmable devices on the module.

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

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MODE Signal State

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High or open

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SD Card

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Low or ground

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QSPI Interface

Table 2: Selecting power-on boot device.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector: 

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Table 1: TE0724-02 main components.

1. XILINX ZYNQ XC7Z020-2CLG400C, U1
2. Gigabit Ethernet Transceiver Alaska 88E1512, U7
3. Power Manager Dialog DA9062, U4
4. 1GByte - 2x 4Gbit DDR3L RAM, U3, U5
5. 32MByte Spansion SPI Flash S25FL256, U13
6. 128KByte Serial EEPROM Microchip 24AA, U10
7.  CAN Transceiver MCP2542FDT, U2
8.  160 Pin Samtec B2B Connector ST5-80-1.50-L-D-P-TR, J1

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

Boot mode is selected via two pins at B2B connector J2. By default the TE0724 supports JTAG and SPI Boot Mode. Connecting a SD Card via B2B connector to MIO Pins 40 to 45 or MIO 46 to 51 gives the possibility to boot from SD Card.

Table 2: Boot mode selection.

Signals, Interfaces and Pins

Table x: General overview of PL I/O signals connected to the B2B connectors.

All PS MIO banks are powered by on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the PS I/Os MIOx, MIOx ... MIOx, ... depend on the carrier board peripherals connected to these pins.

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TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
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<!-- MGTConnections lanesand shouldInterfaces beor listed separately, as they are more specific than just general I/Os. B2B Pin's which are accessible by User   -->

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector: 

Table x: MGT lanes.

Below are listed MGT banks reference clock sources.

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Table 3: General overview of PL I/O signals connected to the B2B connectors.

All PS MIO banks are powered by on-module DC-DC power rails. Valid VCCO_35 should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the PS I/Os MIO40 to MIO51 depend on the carrier board peripherals connected to these pins.

<!--
TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
  -->

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MGT lanes should be listed separately, as they are more specific than just general I/Os.  
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JTAG Interface

JTAG access to the ... ZYNQ is provided through B2B connector .... J1 and testpoints.

Table 54: JTAG interface signals.

System Controller CPLD I/O Pins

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Table x5: System Controller CPLD I/O pins.

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