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Table 3: Pin header J2 signal assignment. *pin 1 on header J2


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Figure 3: J2 pin header signal assignment

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S2ONOFFDefaultDescription
1Normal modeModule update modeONUpdate Mode JTAG access to SC CPLD only
2Do not use (illegal setting)Normal modeOFFDo not change from default, secure configuration EEPROMMust be in OFF state always.
3VIO connected to 3.3VPower VIO from pin header J2OFFSC CPLD User I/O -voltage from/to pin headerVoltage
4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)

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