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Table 3: Pin header J2 signal assignment. *pin 1 on header J2
Top View | Bottom View flipped |
Figure 3: J2 pin header signal assignment
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S2 | ON | OFF | Default | Description |
---|---|---|---|---|
1 | Normal mode | Module update mode | ON | Update Mode JTAG access to SC CPLD only |
2 | Do not use (illegal setting) | Normal mode | OFFDo not change from default, secure configuration EEPROM | Must be in OFF state always. |
3 | VIO connected to 3.3V | Power VIO from pin header J2 | OFF | SC CPLD User I/O -voltage from/to pin headerVoltage |
4 | Power 3.3V from USB | Power 3.3V from pin header J2 | OFF | Power on-board peripherals (FTDI chip & SC CPLD, ...) |
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