Page History
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- MPSoC: ZYNQ UltraScale+ ZU7EV 900-pin package
- Memory
- 64bit DDR4, 8 GByte maximum
- Dual SPI boot Flash in parallel, 512 MByte maximum - User I/Os
- 65 x PS MIOs, 48 x PL HD GPIOs, 156 x PL HP GPIOs (3 banks)
- Serial transceivers: 4 x GTR + 16 x GTH
- Transceiver clocks inputs and outputs
- PLL clock generator inputs and outputs - Si5345 - 10 output PLL
- All power supplies on board, single 3.3V power source required
- 14 on-board DC-DC regulators and 13 LDOs
- LP, FPLPD, FPD, PL separately controlled power domains - Support for all boot modes (except NAND) and scenarios
- Support for any combination of PS connected peripherals
- Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
- B2B connectors: 4 x 160 pin
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Power Rails
Power Rail Name | B2B J1 Pins | B2B J2 Pins | B2B J3 Pins | B2B J4 Pins | Directions | Note |
|---|---|---|---|---|---|---|
| PL_DCIN | 151, 153, 157, 159 | - | - | - | Input | - |
| DCDCIN | - | 154, 156, 158, 160, | - | - | Input | - |
| LP_DCDC | - | 138, 140, 142, 144 | - | - | Input | - |
| PS_BATT | - | 125 | - | - | Input | - |
| GT_DCDC | - | - | 157, 158, 159, 160 | - | Input | - |
| PLL_3V3 | - | - | 152 | - | Input | U5 (programmable PLL) 3.3V nominal input |
| SI_PLL_1V8 | - | - | 151 | - | Output | Internal voltage level 1.8V nominal output |
| PS_1V8 | - | 99 | 147, 148 | - | Output | Internal voltage level |
| PL_1V8 | 91, 121 | - | - | - | Output | Internal voltage level |
| DDR_1V2 | - | 135 | - | - | Output | Internal voltage level |
| VCCO47 | - | - | 43, 44 | - | Input | - |
| VCCO48 | - | - | 15, 16 | - | Input | - |
| VCCO64 | - | - | - | 58, 106 | Input | - |
| VCCO65 | - | - | - | 69, 105 | Input | - |
| VCCO66 | 90, 120 | - | - | - | Input | - |
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