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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEI0015 block diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 910 |
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| diagramName | TEI0015_OV_BD |
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| simpleViewer | false |
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| width | |
|---|
| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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|
|
| Scroll Only |
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|
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| Scroll Title |
|---|
| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
|---|
| Bank 1A | J1 | 7 | 3.3V | AIN0...6 | | Bank 1B | J4 | 5 | 3.3V | JTAG interface | | Bank 2 | J1 | 4 | 3.3V |
D2D6D0| DIO0...1 | | Bank 8 | J2 | 1 | 3.3V | RESET |
|
JTAG Interface
JTAG access to the TEI0015 SoM through pin header connector J4.
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| Scroll Title |
|---|
| anchor | Table_OBP_IOs |
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| title | FPGA I/O Banks |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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|
| Connector Designator | Voltage LevelJ1 | 3.3V| 1x14 Pin header, J1 | AIN0...6 | | 1 | Jumper, J3 | AIN7 | | Bank 1B |
J4 | 3.3V | JTAG interface| 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK | | Bank 2 |
J13.3V| 1x14 Pin header, J1 | D2...5 |
Bank J2 | 9 | 3.3V | D6...14 | | J1 | 2 | 3.3V | D0...1 | Bank 8 | J2 | 1 | 3.3V | RESET| A2D, U15 | ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV |
| 1 | 12MHz Oscillator, U7 | CLK12M |
| 2 | Amplifier, U12 | nIAMP_A0, nIAMP_A1 | | Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD | | Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 | | 2 | 1x14 Pin header, J1 | DIO0...1 | | 1 | D12_R | DIO12 | | Bank 6 | 16 | SDRAM, U2 | DQ0...15 | | 2 | SDRAM, U2 | DQM0...1 | | 1 | D11_R | DIO11 | | Bank 8 | 8 | User Red LEDs, D2...9 | LED0...7 |
| 6 | SPI Flash, U5 | F_CS, F_CK, F_DI, F_DO, nSTATUS, DEVCLRn |
| 1 | Red LED, D10 | CONF_DONE |
| 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 |
| 1 | Push Button, S2 | USER_BTN |
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On-board Peripherals
| Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
...