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| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
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| Address inputs | A0 ... A13 | bank 3 | - | Bank address inputs
| BA0 / BA1 | bank 3 | - | | Data input/output | DQ0 ... DQ15 | bank 6 | - | | Data mask | DQM0 ... DQM1 | bank 6 | - | | Clock | CLK | bank 3 |
| | Control Signals | CS | bank 3 | Chip select | CKE | bank 3 | Clock enable | RAS | bank 3 | Row Address Strobe | CAS | bank 3 | Column Address Strobe | | WE | bank 3 | Write Enable |
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FTDI FT2232H
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
| Scroll Title |
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| anchor | Table_OBP_FTDI |
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| title | FTDI chip interfaces and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
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| Pin 12, ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface | | Pin 13, ADBUS1 | TDI | FPGA bank 1B, pin F5 | | Pin 14, ADBUS2 | TDO | FPGA bank 1B, pin F6 | | Pin 15, ADBUS3 | TMS | FPGA bank 1B, pin G1 | | Pin 32, BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user configurable | | Pin 33, BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | user configurable | | Pin 34, BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user configurable | | Pin 35, BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user configurable | | Pin 37, BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | user configurable | | Pin 38, BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user configurable |
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RTC
| Scroll Title |
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| anchor | Table_OBP_RTC |
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| title | I2C interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U? Pin | Notes |
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| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| DesignatorClock Source | DescriptionSchematic Name | Frequency | Note | MHz | MHz | KHz
|---|
| Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3 Connected to FPGA SoC bank 2, pin H6 |
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Power and Power-On Sequence
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