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Template Revision 1.7 - on construction

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD+Firmware

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Overview

Firmware for PCB-Master CPLD with designator U17. Use first CPLD Device in Chain: LCMX02-1200HC

Firmware for PCB-Slave CPLD with designator U39. Use second CPLD Device in Chain: LCMX02-1200HC

Feature Summary

Power Management (Slave CPLD)
Reset Management (both)
CPLD JTAG (both)
FMC JTAG / PJTAG (Master CPLD)
FMC VADJ Power (Master CPLD)
Boot Mode (Slave CPLD)
PCIe (Slave CPLD)
SD (both)
UART SoC (Slave CPLD)
UART (Debug) (Master CPLD)
CAN (Master CPLD)
USB (Master CPLD)
DisplayPort (Master CPLD)
SFP (Master CPLD)
I2C (Master CPLD)
LEDs (both)
RGPIO (both)

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

todo list of both cplds

Name / opt. VHD Name	Direction	Pin	Bank Power	Description	CPLD	PCB REV02 Exception
C_T1		24	3V3SB	/ currently_not_used	U17	NC
C_T2		26	3V3SB	/ currently_not_used	U17	NC
C_T3		25	3V3SB	/ currently_not_used	U17	NC
C_TCK	in	131	3V3SB	JTAG J28 (XMOD2) / FMC JTAG	U17
C_TDI	in	136	3V3SB	JTAG J28 (XMOD2) / FMC JTAG	U17
C_TDO1 / C_TDO	out	137	3V3SB	JTAG J28 (XMOD2) / FMC JTAG	U17
C_TMS	in	130	3V3SB	JTAG J28 (XMOD2) / FMC JTAG	U17
CAN_FAULT		106	3V3SB	CAN	U17
CAN_RX	in	107	3V3SB	CAN	U17
CAN_S	out	105	3V3SB	CAN	U17
CAN_TX	out	104	3V3SB	CAN	U17
CLK_125MHz / PHY_CLK	in	70	1.8V	/ currently_not_used	U17
CON_NTRST / JTAG_TRST	in	117	3V3SB	JTAG, Connector J30	U17
CON_RTCK / JTAG_RTCK	out	125	3V3SB	JTAG, Connector J30	U17
CON_sRST / JTAG_SRST	in	127	3V3SB	JTAG, Connector J30	U17
CON_TCK / JTAG_TCK	in	122	3V3SB	JTAG, Connector J30	U17
CON_TDI / JTAG_TDI	in	119	3V3SB	JTAG, Connector J30	U17
CON_TDO / JTAG_TDO	out	126	3V3SB	JTAG, Connector J30	U17
CON_TMS / JTAG_TMS	in	121	3V3SB	JTAG, Connector J30	U17
DIR_T1		23	3V3SB	/ currently_not_used	U17	NC
DIR_T2		28	3V3SB	/ currently_not_used	U17	NC
DIR_T3		27	3V3SB	/ currently_not_used	U17	NC
DP_AUX_DE / DP_DE	out	92	3V3SB	Display Port	U17
DP_AUX_RX / DP_RX	in	91	3V3SB	Display Port	U17
DP_AUX_TX / DP_TX	out	93	3V3SB	Display Port	U17
DP_EN	out	77	3V3SB	Display Port	U17
DP_TX_HPD / DP_HPD	in	94	3V3SB	Display Port	U17
ETH_RST	out	62	1.8V	ETH Reset	U17
EX_IO1		112	3V3SB	/ currently_not_used	U17
EX_IO2		113	3V3SB	/ currently_not_used	U17
EX_IO3		114	3V3SB	/ currently_not_used	U17
EX_IO4		115	3V3SB	/ currently_not_used	U17
F2_EN		19	3V3SB	/ currently_not_used	U17	NC
F2PWM		20	3V3SB	/ currently_not_used	U17	NC
F2SENSE		21	3V3SB	/ currently_not_used	U17	NC
FMC_CLK_DIR / FMC_CLKDIR	in	73	3V3SB	FMC	U17
FMC_TCK	out	95	3V3SB	FMC	U17
FMC_TDI	out	96	3V3SB	FMC	U17
FMC_TDO	in	97	3V3SB	FMC	U17
FMC_TMS	out	98	3V3SB	FMC	U17
FMC_VID0	out	139	3V3SB	FMC	U17
FMC_VID1	out	140	3V3SB	FMC	U17
FMC_VID2	out	141	3V3SB	FMC	U17
GND		84	3V3SB	REV03 unconnected / currently_not_used	U17	USB_TRST, other USB HUB
HDIO_SC10 / SC10	out	60	1.8V	FPGA / DP_RX or 'Z'	U17
HDIO_SC11 / SC11	in	59	1.8V	FPGA / DP_DE	U17
HDIO_SC12 / SC12	out	58	1.8V	FPGA / DP_HPD	U17
HDIO_SC13 / SC13	out	57	1.8V	FPGA / RGPIO TX	U17
HDIO_SC14 / SC14	in	56	1.8V	FPGA / RGPIO RX	U17
HDIO_SC15 / SC15	in	55	1.8V	FPGA / RGPIO CLK	U17
HDIO_SC16 / SC16	in	54	1.8V	FPGA / CAN_S	U17
HDIO_SC17 / SC17	in	52	1.8V	FPGA / XMOD LED	U17
HDIO_SC18 / SC18	in	68	1.8V	FPGA / CAN_TX	U17
HDIO_SC19 / SC19	out	69	1.8V	FPGA / CAN_RX	U17
I2C_RST	out	61	1.8V	I2C	U17
JTAGENB		120	3V3SB	external Pin for CPLD Firmware Update	U17
LED_1A / JLED1	out	109	3V3SB	USB3.0 LED Jellow	U17
LED_2A / JLED2A	out	111	3V3SB	USB3.0 LED Green/Orange	U17
LED_2B / JLED2B	out	110	3V3SB	USB3.0 LED Green/Orange	U17
MIO26	out	41	1.8V	MIO / PJTAG	U17
MIO27	out	40	1.8V	MIO / PJTAG	U17
MIO28	in	39	1.8V	MIO / PJTAG	U17
MIO29	out	38	1.8V	MIO / PJTAG	U17
NetU17_103		103	3V3SB	/ currently_not_used	U17
NetU17_129		129	3V3SB	/ currently_not_used	U17
NetU17_15		15	3V3SB	/ currently_not_used	U17
NetU17_17		17	3V3SB	/ currently_not_used	U17
NetU17_31		31	3V3SB	/ currently_not_used	U17
NetU17_63		63	1.8V	/ currently_not_used	U17
NetU17_87		87	3V3SB	/ currently_not_used	U17
NetU17_89		89	3V3SB	/ currently_not_used	U17
OCLK_EN / OSC_EN	out	74	3V3SB	Programmable Oscillator U45	U17
PHY_CONFIG	out	65	1.8V	ETH PHY	U17
PHY_LED0	in	67	1.8V	ETH PHY	U17
PHY_LED1	in	86	3V3SB	ETH PHY	U17
PHY_LED2	in	85	3V3SB	ETH PHY	U17
SC_CLK0 / CLK0	in	76	3V3SB	/ currently_not_used	U17
SC_CLK1 / CLK1	in	75	3V3SB	/ currently_not_used	U17
SC_IO0 / X0	out	50	1.8V	MTS dummy	U17
SC_IO1 / X1	in	49	1.8V	internal cpld RGPIO CLK	U17
SC_IO2 / X2	out	48	1.8V	internal cpld RGPIO TX	U17
SC_IO3 / X3	in	47	1.8V	internal cpld RGPIO RX	U17
SC_IO4 / X4	out	45	1.8V	SD WP to slave cpld	U17
SC_IO5 / X5	in	44	1.8V	STM dummy	U17
SC_IO6 / X6	out	43	1.8V	/ currently_not_used	U17
SC_IO7 / X7	out	42	1.8V	/ currently_not_used	U17
SC_IO8 / X8	in	22	3V3SB	internal cpld RGPIO available(1.8V on)	U17
SC_SCL / SCL	in	14	3V3SB	I2C Mux U27 / currently_not_used	U17
SC_SDA / SDA	in	13	3V3SB	I2C Mux U27 / currently_not_used	U17
SC2_SW3 / SW3	in	6	3V3SB	DIP-Switch S5-3	U17
SC2_SW4 / SW4	in	5	3V3SB	DIP-Switch S5-4	U17
SD_WP	in	100	3V3SB	MMC SDWP	U17
SFP_LED1 / SFP_LED0	out	81	3V3SB	SFP	U17
SFP_LED2 / SFP_LED1	out	82	3V3SB	SFP	U17
SFP_LED3 / SFP_LED2	out	78	3V3SB	SFP	U17
SFP_LED4 / SFP_LED3	out	83	3V3SB	SFP	U17
SFP1_LOS		32	3V3SB	SFP / currently_not_used	U17
SFP1_TX_DIS	out	33	3V3SB	SFP	U17
SFP2_LOS		35	3V3SB	SFP / currently_not_used	U17
SFP2_TX_DIS	out	34	3V3SB	SFP	U17
STAT_LED0 / LED0	out	99	3V3SB	LED D4 Green	U17
STAT_LED1 / LED1	out	128	3V3SB	LED D1 Red	U17
USB0_RST / USB_TRST		71	1.8V	USB (U9) PHY Reset	U17
USBH_LED_G3		11	3V3SB	USB Hub (U4) / currently_not_used	U17
USBH_LED_G4		12	3V3SB	USB Hub (U4) / currently_not_used	U17
USBH_LED_SS1		9	3V3SB	USB Hub (U4) / currently_not_used	U17
USBH_LED_SS2		133	3V3SB	USB Hub (U4) / currently_not_used	U17
USBH_LED_SS3		132	3V3SB	USB Hub (U4) / currently_not_used	U17
USBH_LED_SS4		138	3V3SB	USB Hub (U4) / currently_not_used	U17
USBH_MODE0	out	142	3V3SB	USB Hub (U4)	U17
USBH_MODE1	out	143	3V3SB	USB Hub (U4)	U17
USBH_RST	out	10	3V3SB	USB Hub (U4)	U17
XMOD1_A / XMOD_TXD	out	3	3V3SB	J28 (XMOD 2 UART)	U17
XMOD1_B / XMOD_RXD	in	2	3V3SB	J28 (XMOD 2 UART)	U17
XMOD1_E / XMOD_E	out	4	3V3SB	J28 (XMOD 2 LED)	U17
XMOD1_G / XMOD_G	out	1	3V3SB	J28 (XMOD 2 Button)	U17
1.8V_EN / EN_1V8	out	106	3V3SB	Enable 1.8V Power	U39
5V_EN / EN_5V	out	115	3V3SB	Enable 5V Power, can be permanently enabled by S4-4	U39
C_TCK		131	3V3SB	JTAG J28 (XMOD2) / currently_not_used	U39
C_TDO		137	3V3SB	JTAG J28 (XMOD2) / currently_not_used	U39
C_TDO1		136	3V3SB	JTAG J28 (XMOD2) / currently_not_used	U39
C_TMS		130	3V3SB	JTAG J28 (XMOD2) / currently_not_used	U39
CLK_A / AUD_CLK	out	1	1.8V	AUDIO U3 CLK	U39
CLK_CPLD / MEMS_CLKIN	in	128	3V3SB	U25 24,576MHz	U39
DONE	in	67	1.8V	PS Done	U39
EN_DDR	out	86	3V3SB	Enable Module DDR Power	U39
EN_FMC / FMC_EN	out	104	3V3SB	FMC	U39
EN_FPD	out	81	3V3SB	Enable Module PS FPD Power	U39
EN_GT_L	out	77	3V3SB	Enable Module GT Power	U39
EN_GT_R	out	93	3V3SB	Enable Module GT Power	U39
EN_LPD	out	84	3V3SB	Enable Module PS LPD Power	U39
EN_PL	out	95	3V3SB	Enable Module PL Power	U39
EN_PLL_PWR	out	78	3V3SB	Enable Module SI5345 Power	U39
EN_PSGT / EN_PSGTR	out	75	3V3SB	Enable Module PS GT Power	U39
ERR_OUT / ERROR	in	70	1.8V	Module PS Error Out / Status	U39
ERR_STATUS / ERR_STAT	in	69	1.8V	Module PS Error Status	U39
F1PWM	out	121	3V3SB	FAN1	U39
F1SENSE	in	125	3V3SB	FAN1	U39
FAN_FMC_EN / FMC_FAN_EN		132	3V3SB	FMC FAN	U39
FMC_PG_C2M	out	141	3V3SB	FMC PG	U39
HD_LED_N / HDLED_N	out	112	3V3SB	J10 HD LED	U39
HD_LED_P / HDLED_P	out	110	3V3SB	J10 HD LED	U39
HDIO_SC0 / SC0	in	32	1.8V	FPGA IO / forward to HD_LED_P / HDLED_P	U39
HDIO_SC1 / SC1	in	33	1.8V	/ currently_not_used	U39
HDIO_SC2 / SC2	in	34	1.8V	/ currently_not_used	U39
HDIO_SC3		35	1.8V	/ currently_not_used	U39
HDIO_SC4		25	1.8V	/ currently_not_used	U39
HDIO_SC5 / SC5	out	26	1.8V	FPGA IO / RGPIO	U39
HDIO_SC6 / SC6	in	27	1.8V	FPGA IO / RGPIO CLK	U39
HDIO_SC7 / SC7	in	28	1.8V	.FPGA IO / RGPIO	U39
I2C_SCL / SCL	in	50	1.8V	I2C / currently_not_used	U39
I2C_SDA / SDA	in	52	1.8V	I2C / currently_not_used	U39
INIT_B / INIT	in	68	1.8V	Module PS Init_B	U39
JTAGENB		120	3V3SB	external Pin for CPLD Firmware Update	U39
LP_GOOD / PG_LPD	in	83	3V3SB	Module LP Power Good	U39
MIO24		38	1.8V	MIO / currently_not_used	U39
MIO25		39	1.8V	MIO / currently_not_used	U39
MIO30	in	48	1.8V	MIO	U39
MIO31	in	49	1.8V	MIO	U39
MIO32		40	1.8V	MIO / currently_not_used	U39
MIO33		41	1.8V	MIO / currently_not_used	U39
MIO34		42	1.8V	MIO / currently_not_used	U39
MIO35		43	1.8V	MIO / currently_not_used	U39
MIO36		44	1.8V	MIO / currently_not_used	U39
MIO37		45	1.8V	MIO / currently_not_used	U39
MIO40	in	54	1.8V	MIO	U39
MIO41		55	1.8V	MIO / currently_not_used	U39
MIO42	out	60	1.8V	MIO	U39
MIO43	in	61	1.8V	MIO	U39
MIO44		47	1.8V	MIO	U39
MOD_EN	out	119	3V3SB	Enable Main Module Power 3.3V	U39
MODE0	out	6	1.8V	Module Boot Mode	U39
MODE1	out	9	1.8V	Module Boot Mode	U39
MODE2	out	10	1.8V	Module Boot Mode	U39
MODE3	out	11	1.8V	Module Boot Mode	U39
MR / MRESETn	out	92	3V3SB	Module PS Power Reset	U39
NetU39_103		103	3V3SB	/ currently_not_used	U39
NetU39_129		129	3V3SB	/ currently_not_used	U39
NetU39_15		15	1.8V	/ currently_not_used	U39
NetU39_17		17	1.8V	/ currently_not_used	U39
NetU39_31		31	1.8V	/ currently_not_used	U39
NetU39_63		63	1.8V	/ currently_not_used	U39
NetU39_87		87	3V3SB	/ currently_not_used	U39
NetU39_89		89	3V3SB	/ currently_not_used	U39
PCI_SFP_EN	out	76	3V3SB	SFP	U39
PER_EN	out	117	3V3SB	Enable 3.3V power	U39
PERST / PERSTn	out	139	3V3SB	PCIE Resetn	U39
PG_DDR	in	91	3V3SB	Module Power Good	U39
PG_FPD	in	85	3V3SB	Module Power Good	U39
PG_GT_L	in	96	3V3SB	Module Power Good	U39
PG_GT_R	in	94	3V3SB	Module Power Good	U39
PG_PL	in	82	3V3SB	Module Power Good	U39
PG_PLL_1V8 / PG_PLL	in	73	3V3SB	Module Power Good	U39
PG_PSGT	in	74	3V3SB	Module Power Good	U39
PLL_LOLn / PLL_LOL	in	58	1.8V	Module PLL / currently_not_used	U39
PLL_RST / PLL_RSTn	out	56	1.8V	Module PLL Reset	U39
PLL_SEL0	out	57	1.8V	Module PLL	U39
PLL_SEL1	out	59	1.8V	Module PLL	U39
POK_1V8	in	107	3V3SB	Carrier Power Good	U39
POK_FMC	in	99	3V3SB	FMC Power Good	U39
PROG_B	OUT	71	1.8V	Module PS_PROG_B	U39
PSON	out	105	3V3SB	ATX J20 PS_ON_N	U39
PWR_BTN	in	113	3V3SB	Power Button S1 or J10	U39
PWRLED_N / LED_N	out	111	3V3SB	J10 PWR	U39
PWRLED_P / LED_P	out	109	3V3SB	J10 PWR	U39
PWROK	in	100	3V3SB	ATX J20 PWROK	U39
RST_BTN	in	114	3V3SB	Reset Button S2 or J10	U39
S_1		127	3V3SB	/ currently_not_used	U39
SC_IO0 / X0	in	12	1.8V	MTS dummy	U39
SC_IO1 / X1	out	13	1.8V	internal cpld RGPIO CLK	U39
SC_IO2 / X2	in	14	1.8V	internal cpld RGPIO RX	U39
SC_IO3 / X3	out	20	1.8V	internal cpld RGPIO TX	U39
SC_IO4 / X4	in	21	1.8V	MMC SD WP from master	U39
SC_IO5 / X5	out	22	1.8V	STM dummy	U39
SC_IO6 / X6	in	23	1.8V	/ currently_not_used	U39
SC_IO7 / X7	in	24	1.8V	/ currently_not_used	U39
SC_IO8 / X8	out	126	3V3SB	internal cpld RGPIO available(1.8V on)	U39
SC2_SW1 / SW1	in	133	3V3SB	S5-1 / Boot Mode Selection	U39
SC2_SW2 / SW2	in	138	3V3SB	S5-2 / Boot Mode Selection	U39
SD_A_EN	out	140	3V3SB	Micro SD	U39
SD_B_EN	out	122	3V3SB	MMC SD	U39
SD_CD / SD_CD_OUT	out	65	1.8V	SD Card detect to FPGA	U39
SD_CD_B	in	143	3V3SB	MMC SD CD	U39
SD_CD_S	in	142	3V3SB	Micro SD CD	U39
SEL_SD / SD_SEL	out	62	1.8V	SD select (Mirco or MMC)	U39
SRST_B / SRSTn	out	19	1.8V	Module PS_SRST_B	U39
STAT_LED2 / LED2	out	98	3V3SB	LED D6 Green	U39
STAT_LED3 / LED3	out	97	3V3SB	LED D7 Red	U39
XMOD2_A / XMOD_TXD	out	5	1.8V	J12 (XMOD 1 UART)	U39
XMOD2_B / XMOD_RXD	in	4	1.8V	J12 (XMOD 1 UART)	U39
XMOD2_E / XMOD_LED	out	3	1.8V	J12 (XMOD 1 LED)	U39
XMOD2_G / XMOD_BTN	in	2	1.8V	J12 (XMOD 1 Button)	U39

Functional Description

JTAG

JTAGENB set carrier board CPLD into the chain for firmware update. For Update set DIP S4-3 to ON.

Power

FMC VADJ is handled on master CPLD.

DIP	Positon	Description
S5-4	ON	1.8V
S5-4	OFF	1.2V

Power on and off sequencing is done with slave CPLD

Scroll Title

anchor	Figure_power
title	Power On/OFF Sequencing

draw.io Diagram

border	true
viewerToolbar	true

fitWindow	false
diagramName	power_seq
simpleViewer	false
width
diagramWidth	2199
revision	3

Reset

Power, Zynq reset and PCIe is handle on Slave CPLD

USB, I2C Reset is handled on Master CPLD

todo description

CPLD JTAG

todo (both)

FMC JTAG / PJTAG

todo (Master CPLD)

Boot Mode

todo (Slave CPLD)

PCIe

todo (SlaveCPLD)

SD

todo (both)

UART SoC

todo (SlaveCPLD)

UART (Debug)

todo todo (Master CPLD)

CAN

todo (Master CPLD)

USB

todo (Master CPLD)

DisplayPort

todo todo (Master CPLD)

SFP

todo todo (Master CPLD)

I2C

todo todo (Master CPLD)

LEDs

todo (both)

RGPIO

todo (both)

Appx. A: Change History and Legal Notices

Revision Changes

Master

Slave

CPLD REV06 to REV07

complete rework
add inter CPLD RGPIO
new LED debugging sequencing
simple UART output with Revision Number and some statistic on second XMOD

CPLD REV05 to REV06

BUGFIX: renamed SC19 to SC17
Connect FMC JTAG to XMOD2 JTAG
Connect PJTAG0 (MIO29..26) to JTAG Pin Header J30
Connect CAN to PL
RGPIO Pin changes

CPLD REV04 to REV05

SD WP
XMOD LED access over PL

Older Revision (PCB REV03) to CPLD REV04

Fix USB HUB Mode default state over RGPIO
Invert JLED2B over RGPIO

Older Revision (PCB REV02) to CPLD REV04

Add all functionality from older Revision (PCB REV03)

CPLD REV06 to REV07

complete rework
add variants (power up and SD)multi-functions for buttons
power on and power downs sequencing
- module complete disable on power down
- power on sequencing
- power down sequencing --> can be forced with power button (hold longer)
Soft PS or PS POR Reset on Reset button (hold longer for PS POR Reset)
add inter CPLD RGPIO
new SoC RGPIO Pinout
removed reboot for pcie initialization
new LED debugging sequencing
Disabled UART on power down state
bugfix WP pin for microSD slot
removed PCIe Reboot.

CPLD REV05 to REV06

LED Status changes of LED D2 D3 and HD_LED, XMOD LED
extended Power Management

CPLD REV04 to REV05

PS reboot via FSBL over MIO30 (need for proper PCI initialization on first power on without press Reset Button)
SD Boot from micoSD only if switch S5-1/-2 is selected to ON
RGPIO connection
Add SD WP to FPGA
Power, Rest Button debounced
direct LED access via MIO and PL

Older Revision (PCB REV03) to CPLD REV04

Bugfix: PCIe Reset Pin location.
Bugfix: Swapping HDLED and PWRLED location.
Bugfix: MEMS_CLKIN Pin location.
Add XMOD 1 LED

Older Revision (PCB REV02) to CPLD REV04

Add all functionality from older Revision (PCB REV03)

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Note this list must be only updated, if the document is online on public doc!
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Date

Document Revision

CPLD Firmware Revision

Supported PCB Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

	current-version
	current-version
prefix	v.

REV07

REV03,REV04*

Page info

	modified-user
	modified-user

Work in progress
*please write to Trenz Electronic support for PCB REV02

2017-06-07

v.1

Page info

	created-user
	created-user

Initial release (combine Master and Slave CPLD description )

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Trenz Electronic Documentation

Versions Compared

Old Version 7

New Version 8

Key

Table of contents

Overview

Feature Summary

Firmware Revision and supported PCB Revision

Product Specification

Port Description

Functional Description

JTAG

Power

Reset

CPLD JTAG

FMC JTAG / PJTAG

Boot Mode

PCIe

SD

UART SoC

UART (Debug)

CAN

USB

DisplayPort

SFP

I2C

LEDs

RGPIO

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

Legal Notices