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Intel® MAX 10 Commercial [10M08SAU169C8G]
SDRAM Memory up to 64Mb, 166MHz
Dual High Speed USB to Multipurpose UART/FIFO IC
64 Mb Quad SPI Flash
4Kb EEPROM Memory
8x User LED
Micro USB2 Receptacle 90
18 Bit 2MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface:
Power Supply:
Dimension: 86.5mm x 25mm
Others:
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anchor | Figure_OV_BD |
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title | TEI0015 block diagram |
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fitWindow | false |
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lbox | true |
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revision | 2022 |
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diagramName | TEI0015_OV_BD |
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simpleViewer | false |
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SMA Connector, J5...6
Amplifier, U12- U14- U6
Series Voltage Reference, U8
Analog to Digital Convertor, U15
Voltage Regulator, U10- U13- U16
Switching Voltage Regulator, U11- U4
SDRAM Memory, U2
- Intel® MAX 10, U1
SDRAM Memory, U2
Active serial Memory, U5
12.00 MHz MEMS oscillator, U7
FTDI USB2 to JTAG/UART adapter, U3
User LEDs, D2...9
4Kb EEPROM, U9
Configuration LED (Red) , D10
Power-on LED (Green), D1
Push button, S1...2
Micro USB2 Receptacle, J9
1x14 pin header (Not assembled), J2
1x6 pin header (Not assembled), J4
Jumper, J3
1x14 pin header (Not assembled), J1
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anchor | Table_OBP_IOs |
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title | FPGA I/O Banks |
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FPGA Bank | I/O Signal Count | Connected to | Notes |
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Bank 1A | 7 | 1x14 Pin header, J1 | AIN0...6 | 1 | Jumper, J3 | AIN7 | Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK | Bank 2
| 4 | 1x14 Pin header, J1 | D2...5 | 5 | A2D, U15 | ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV | 1 | 12MHz Oscillator, U7 | CLK12M | 2 | Amplifier, U12 | nIAMP_A0, nIAMP_A1 | Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD | Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 | 2 | 1x14 Pin header, J1 | DIO0...1 | 1 | D12_R | DIO12 | Bank 6 | 16 | SDRAM, U2 | DQ0...15 | 2 | SDRAM, U2 | DQM0...1 | 1 | D11_R | DIO11 | Bank 8
| 8 | User Red LEDs, D2...9 | LED0...7 | 6 | SPI Flash, U5 | F_CS, F_CKCKL, F_DI, F_DO, nSTATUS, DEVCLRn | 1 | Red LED, D10 | CONF_DONE | 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 | 1 | Push Button, S2 | USER_BTN |
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anchor | Table_OBP |
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title | On board peripherals |
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cellHighlighting | true |
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anchor | Table_OBP_FTDI |
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title | FTDI chip interfaces and pins |
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orientation | portrait |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
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ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface | ADBUS1 | TDI | FPGA bank 1B, pin F5 | ADBUS2 | TDO | FPGA bank 1B, pin F6 | ADBUS3 | TMS | FPGA bank 1B, pin G1 | BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user configurable | BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | user configurable | BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user configurable | BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user configurable | BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | user configurable | BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user configurable |
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SPI Flash
On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
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anchor | Table_OBP_A2D |
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title | A2D converter interface and pins |
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Pins | Connected to | Notes |
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IN+ | Diff Amplifier U14, VOUT- |
| IN- | Diff Amplifier U14, VOUT+ |
| SDI | Bank 2FPGA, bank 2, pin M2, ADC_SDI |
| SDOBank | FPGA, bank 2, ADCpin M1, ADC_SDO |
| SCKBank | FPGA, bank 2, ADCpin N3, ADC_SCK |
| CNV | Bank FPGA, bank 2, pin N2, ADC_CNV |
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LEDs
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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Designator | Color | Connected to | Active Level | Note |
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D2...9 | Red | LED1...8 | Active High | User LEDs | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | D1 | Green | 3.3V | Active High | After power on it will be on |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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fitWindow | false |
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diagramDisplayName | TEI0015_PWR_P |
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lbox | true |
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revision | 1011 |
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diagramName | TEI0015_PWR_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 638 |
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anchor | Table_PWR_BV |
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title | Zynq Intel MAX SoC bank voltages. |
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orientation | portrait |
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sortEnabled | false |
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| Schematic Name | | Notes |
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Bank 1A | VCCIO1A | 3.3V |
| Bank 1B | VCCIO1B | 3.3V |
| Bank 2 | VCCIO2 | 3.3V |
| Bank 3 | VCCIO3 | 3.3V |
| Bank 5 | VCCIO5 | 3.3V |
| Bank 6 | VCCIO6 | 3.3V |
| Bank 8 | VCCIO8 | 3.3V |
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anchor | Table_TS_AMR |
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title | Absolute maximum ratings |
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orientation | portrait |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Symbols | Description | Min | Max | Unit | Reference Document |
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VIN | Supply voltage | 4.75 | 5.25 | V |
| VCC_ONE | Supply voltage for core and periphery through on-die voltage regulator | -0.5 | 3.9 | V | Intel MAX 10 datasheet | VCCIO | Supply voltage for input and output buffersbufferse | -0.5 | 3.9 | V | Intel MAX 10 datasheet | VCCA | Supply voltage for phase-locked loop (PLL) regulator and ADC | -0.5 | 3.9 | V | Intel MAX 10 datasheet | V_AN_IN | Analog Input Voltage on ADC IC U15 pins | –0.3 | 5.4 | V | AD4003BCPZ datasheet | V_REF | Analog reference voltage on IC U15 | -0.3 | 6 | V | AD4003BCPZ datasheet | T_STG | Storage Temperature | -25 | +85 | °C |
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