Page History

Important General Note:

• Export PDF to download, if vivado revision is changed!

• Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

  • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    • Figure template (note: inner scroll ignore/only only with drawIO object):

      Scroll Title
      anchor Figure_xyz title Text
      Scroll Ignore Create DrawIO object here: Attention if you copy from other page, use Scroll Only image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      
      

    • Table template:

      • Layout macro can be use for landscape of large tables
      • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

    • 
      

      Scroll Title
      anchor Table_xyz title Text
      Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Example Comment 1 2

      
      

• ...

Notes :

• short description of the design

• Short Link of "Scroll only" macro:

  • Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info

  • List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Notes :

• Add basic key futures, which can be tested with the design

• Vitis/Vivado 2019.2
• PetaLinux
• Linux Debian 9 (Stretch) or Linux Ubuntu 18.04 (Bionic Beaver)
• HDMI
• SD
• ETH (use EEPROM MAC)
• USB
• I2C
• TE0701
• RTC
• Modified FSBL for SI5338 programming and DMA (for HDMI)
• Special FSBL for QSPI programming

Notes :

• add every update file on the download
• add design changes on description

• add known Design issues and general notes for the current revision
• do not delete known issue, add fixed version time stamp if  issue fixed

Notes :

• list of software which was used to generate the design

Notes :

• list of software which was used to generate the design

Notes :

• content of the zip file

Notes :

• prebuilt files
• Template Table:

  • 
    

    Scroll Title
    anchor Table_PF title Prebuilt files
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Hardware-Platform-Specification-Files *.xsa Exported Vivado Hardware Specification for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems SREC-File *.srec Converted Software Application for MicroBlaze Processor Systems

    
    

• Basic Design Steps

• Add/ Remove project specific description

Note:

• Programming and Startup procedure

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Note:

• Add picture of HW Manager

• add notes for the signal either groups or topics, for example:
  

  Control:

  • add controllable IOs with short notes..

  Monitoring:

  • add short notes for signals which will be monitored only
  • SI5338 CLKs:
    • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
    • expected CLK Frequ:...
      

Note:

• Description of Block Design, Constrains... BD Pictures from Export...

Note:

• optional for Zynq / ZynqMP only

• add basic PS configuration

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

 TODO replace loc constrains with correct one for TE0820
#
# TE0701 I2C Bus
#
set_property PACKAGE_PIN P7 [get_ports IIC_1_scl_io]
set_property PACKAGE_PIN P6 [get_ports IIC_1_sda_io]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_1_scl_io]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_1_sda_io]

#
# ADV7511 Interface
#
set_property PACKAGE_PIN L6 [get_ports hdmi_out_clk]
set_property PACKAGE_PIN L7 [get_ports hdmi_out_de]
set_property PACKAGE_PIN K4 [get_ports hdmi_out_hsync]
set_property PACKAGE_PIN K3 [get_ports hdmi_out_vsync]
set_property PACKAGE_PIN T6 [get_ports {hdmi_out_data[0]}]
set_property PACKAGE_PIN R6 [get_ports {hdmi_out_data[1]}]
set_property PACKAGE_PIN V9 [get_ports {hdmi_out_data[2]}]
set_property PACKAGE_PIN U9 [get_ports {hdmi_out_data[3]}]
set_property PACKAGE_PIN T7 [get_ports {hdmi_out_data[4]}]
set_property PACKAGE_PIN N8 [get_ports {hdmi_out_data[5]}]
set_property PACKAGE_PIN R7 [get_ports {hdmi_out_data[6]}]
set_property PACKAGE_PIN N9 [get_ports {hdmi_out_data[7]}]
set_property PACKAGE_PIN Y8 [get_ports {hdmi_out_data[8]}]
set_property PACKAGE_PIN V8 [get_ports {hdmi_out_data[9]}]
set_property PACKAGE_PIN W8 [get_ports {hdmi_out_data[10]}]
set_property PACKAGE_PIN U8 [get_ports {hdmi_out_data[11]}]
set_property IOSTANDARD LVCMOS18 [get_ports hdmi_*]

set_property PACKAGE_PIN H7 [get_ports {cec_clk[0]}]
set_property PACKAGE_PIN M8 [get_ports {ct_hpd[0]}]
set_property PACKAGE_PIN J7 [get_ports {ls_oe[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {cec_clk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {ct_hpd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {ls_oe[0]}]

• optional chapter separate

• sections for different apps

• optional chapter separate

• sections for linux

• Add "No changes." or "Activate: and add List"

/include/ "system-conf.dtsi"
/ {
	chosen {
    		xlnx,eeprom = &eeprom;
		    bootargs= "console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=256M";

  	};
};


/ {
	#address-cells = <2>;
	#size-cells = <2>;
	memory@0{
	  device-type = "memory";
	  reg = <0x000000000 0x00000000 0x00000000 0x80000000>;
	};	
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		hdmi_fb_reserved_region: framebuffer@7FC00000 {
		    compatible = "removed-dma-pool";
		    //compatible = "shared-dma-pool";
		    //compatible = "xlnx,reserved-memory";
		    no-map;
		    reg = <0x0 0x7FC00000 0x0 0x400000>;
		};
      	};
 
	hdmi_fb: framebuffer@0x7FC00000 {           // HDMI out
		compatible = "simple-framebuffer";
		reg = <0x0 0x7FC00000 0x0 (1280 * 720 * 4)>;    // 720p
		width = <1280>;                         // 720p
		height = <720>;                         // 720p
		stride = <(1280 * 4)>;                  // 720p
		format = "a8b8g8r8";
		status = "okay";
	};
};

&axi_vdma_0 {
   status = "disabled";
};
  
&v_tc_0 {
    //xilinx-vtc: probe of 43c20000.v_tc failed with error -2
    status = "disabled";
};

/* SDIO */

&sdhci1 {
   status = "okay";
   disable-wp;
   no-1-8-v;
};

/* ETH PHY */
&gem3 {

	status = "okay";
  ethernet_phy0: ethernet-phy@0 {
		compatible = "marvell,88e1510";
		device_type = "ethernet-phy";
    		reg = <1>;
	};
};
/* USB 2.0 */
 
/* USB  */
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
 	 snps,dis_u2_susphy_quirk;
  	snps,dis_u3_susphy_quirk;
};
   
&usb0 {
    status = "okay";
    /delete-property/ clocks;
    /delete-property/ clock-names;
    clocks = <0x3 0x20>;
    clock-names = "bus_clk";
};




/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

&i2c0 {
  eeprom: eeprom@50 { 
     compatible = "atmel,24c08";
     reg = <0x50>;
  };
};

• Add description for other Software, for example SI CLK Builder ...
• SI5338 and SI5345 also Link to:
  • Si5345
  • Si5338