...
...
Scroll Title |
---|
anchor | Figure_OV_BD |
---|
title | TEI0015 block diagram |
---|
|
Scroll Ignore |
---|
draw.io Diagram |
---|
border | false |
---|
viewerToolbar | true |
---|
| |
---|
fitWindow | false |
---|
diagramDisplayName | |
---|
lbox | true |
---|
revision | 1920 |
---|
diagramName | TEI0015_OV_BD |
---|
simpleViewer | false |
---|
width | |
---|
links | auto |
---|
tbstyle | hidden |
---|
diagramWidth | 641 |
---|
|
|
Scroll Only |
---|
|
|
...
Scroll Title |
---|
anchor | Table_OBP_IOs |
---|
title | FPGA I/O Banks |
---|
|
FPGA Bank | I/O Signal Count | Connected to | Notes |
---|
Bank 1A | 7 | 1x14 Pin header, J1 | AIN0...6 | 1 | Jumper, J3 | AIN7 | Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK | Bank 2
| 4 | 1x14 Pin header, J1 | D2...5 | 5 | A2D, U15 | ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV | 1 | 12MHz Oscillator, U7 | CLK12M | 2 | Amplifier, U12 | nIAMP_A0, nIAMP_A1 | Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD | Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 | 2 | 1x14 Pin header, J1 | DIO0...1 | 1 | D12_R | DIO12 | Bank 6 | 16 | SDRAM, U2 | DQ0...15 | 2 | SDRAM, U2 | DQM0...1 | 1 | D11_R | DIO11 | Bank 8
| 8 | User Red LEDs, D2...9 | LED0...7 | 6 | SPI Flash, U5 | F_CS, F_CK, F_DI, F_DO, nSTATUS, DEVCLRn | 1 | Red LED, D10 | CONF_DONE | 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 | 1 | Push Button, S2 | USER_BTN |
|
Micro
...
USB2.0 Connector
The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.
Scroll Title |
---|
anchor | Table_OBP_USB |
---|
title | Micro USB-2 connector pins |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Pins | Connected to | Note |
---|
VBUS | USB_VBUS | It is connected to GND | D+ | FTDI FT2232H U3, DP pin |
| D- | FTDI FT2232H U3, DM pin |
|
|
JTAG Interface
JTAG access to the TEI0015 SoM through pin header connector J4.
Scroll Title |
---|
anchor | Table_SIP_JTG |
---|
title | JTAG pins connection |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
JTAG Signal | Pin Header Connector | Note |
---|
TMS | J4-6 |
| TDI | J4-5 |
| TDO | J4-4 |
| TCK | J4-3 |
| JTAG_EN | J4-2 |
|
|
On-board Peripherals
Page properties |
---|
|
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
...
Scroll Title |
---|
anchor | Table_OBP_SDRAM |
---|
title | SDRAM interface IOs and pins |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
---|
Address inputs | A0 ... A13 | bank 3 | - | Bank address inputs
| BA0 / BA1 | bank 3 | - | Data input/output | DQ0 ... DQ15 | bank 6 | - | Data mask | DQM0 ... DQM1 | bank 6 | - | Clock | CLK | bank 3 |
| Control Signals | CS | bank 3 | Chip select | CKE | bank 3 | Clock enable | RAS | bank 3 | Row Address Strobe | CAS | bank 3 | Column Address Strobe | WE | bank 3 | Write Enable |
|
FTDI FT2232H
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip. FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
...
The TEI0015 board is equipped with the Analog Devices AD4003BCPZ, 18the 18-bit 2MSPS ADC provided by Analog Devices, .
Scroll Title |
---|
anchor | Table_OBP_A2D |
---|
title | A2D converter interface and pins |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Pins | Connected to | Notes |
---|
IN+ | Diff Amplifier U14, VOUT- |
| IN- | Diff Amplifier U14, VOUT+ |
| SDI | Bank 2, ADC_SDI |
| SDO | Bank 2, ADC_SDO |
| SCK | Bank 2, ADC_SCK |
| CNV | Bank 2, ADC_CNV |
|
|
...
Scroll Title |
---|
anchor | Table_OBP_LED |
---|
title | On-board LEDs |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Designator | Color | Connected to | Active Level | Note |
---|
D2...9 | Red | LED1...8 | Active High | User LEDs | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | D1 | Green | 3.3V Power Rail3V | Active High | After power on it will be on |
|
...
Push Bottuns
Scroll Title |
---|
anchor | Table_OBP_CLKLED |
---|
title | OsillatorsOn-board Push Buttons |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Designator | Connected to | Functionality |
---|
Clock Source | Schematic Name | Frequency | Note |
---|
S1 | RESET | General reset |
| S2 | USER_BTN | User push button | Connected to Bank 8 |
|
Clock Sources
Scroll Title |
---|
anchor | Table_OBP_CLK |
---|
title | Osillators |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Clock Source | Schematic Name | Frequency | Note |
---|
Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3 | Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3 Connected to FPGA SoC bank 2, pin H6 |
|
...
There is no specific or special power-on sequence, just one single power source is needed. After power on the Green LED (D1) must will be on.
Power Rails
Scroll Title |
---|
anchor | Table_PWR_PR |
---|
title | Module power rails. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Connector Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Notes |
---|
J2
| VIN | 5V | Input |
| 3.3V | 3.3V | Output |
| 5V | 5V | Output |
| J9 | USB_VBUS | 5V | Input |
|
|
...
Scroll Title |
---|
anchor | Table_TS_AMR |
---|
title | Absolute maximum ratings |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Symbols | Description | Min | Max | Unit | Reference Document |
---|
VIN | Supply | VIN supply voltage | 4.75 | 5.25 | V |
| VCC_ONE | Supply voltage for core and periphery through on-die voltage regulator | -0.5 | 3.9 | VI/O Input voltage for FPGA I/O bank | Intel MAX 10 datasheet | VCCIO | Supply voltage for input and output buffers | -0.5 | 3.9 |
|
| VCCA | Supply voltage for phase-locked loop (PLL) regulator and analog-todigital converter (ADC) block (analog) | -0.5 | 43. | 129 |
|
| V | Intel MAX 10 datasheet_AN_IN | Analog Input Voltage on ADC IC U15 pins | –0.3 | 5.4 | V | AD4003BCPZ datasheet | V_REF | Analog reference voltage on IC U15 | 2-0.435 | .16 | V | AD4003BCPZ datasheet | Storage Temperature |
| -25 | +85 | °C |
|
|
...
Scroll Title |
---|
anchor | Table_TS_ROC |
---|
title | Recommended operating conditions. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Symbols | Min | Max | Unit | Reference Document |
---|
VIN supply voltage (5.0V nominal) | 4.75 | 5.25 | V | I/O Input voltage for FPGA I/O bank | -0.5 | 3.6 | V | Intel MAX 10 datasheet | Analog Input Voltage on ADC IC U15 pins | 0 | 3.6 | V | AD4003BCPZ datasheet | | 4.75 | 5.25 | V |
| VCC_ONE | 3.135 | 3.456 | V | see Intel MAX 10 datasheet | VCCIO | 3.135 | 3.456 | V | see Intel MAX 10 datasheet | VCCA | 3.135 | 3.456 | V | see Intel MAX 10 datasheet | V_AN_IN | -0.1 | 5.1 | V | see AD4003BCPZ datasheet | V_REF | 2.4 | 5.1 | V | see | Analog reference voltage on IC U15 | 1 | 3.3 | V | AD4003BCPZ datasheet | Storage Temperature | 0 | +70 | °C | W9864G6JT-6 datasheet |
|
Physical Dimensions
Module size: 25 mm × 86.5 mm × 25 mm. Please download the assembly diagram for exact numbers.
...
Scroll Title |
---|
anchor | Table_RH_HRH |
---|
title | Hardware Revision History |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Date | Revision | Changes | Documentation Link |
---|
2019-02-0611 | 01 | - | REV01 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
...