Page History

CPLD REV06 to REV07

• complete rework

• add inter CPLD RGPIO

• new LED debugging sequencing

• simple UART output with Revision Number and some statistic on second XMOD

CPLD REV05 to REV06

• BUGFIX: renamed SC19 to SC17
• Connect FMC JTAG to XMOD2 JTAG
• Connect PJTAG0 (MIO29..26) to JTAG Pin Header J30
• Connect CAN to PL
• RGPIO Pin changes

CPLD REV04 to REV05

• SD WP
• XMOD LED access over PL

Older Revision (PCB REV03) to CPLD REV04

• Fix USB HUB Mode default state over RGPIO
• Invert JLED2B over RGPIO

Older Revision (PCB REV02) to CPLD REV04

• Add all functionality from older Revision (PCB REV03)

CPLD REV06 to REV07

• complete rework
• add variants (power up and SD)multi-functions for buttons
• power on and power downs sequencing
  • module complete disable on power down
  • power on sequencing
  • power down sequencing --> can be forced with power button (hold longer)
• Soft PS or PS POR Reset on Reset button (hold longer for PS POR Reset)
• add inter CPLD RGPIO
• new SoC RGPIO Pinout
• removed reboot for pcie initialization
• new LED debugging sequencing
• Disabled UART on power down state
• bugfix WP pin for microSD slot
• removed PCIe Reboot.

CPLD REV05 to REV06

• LED Status changes of LED D2 D3 and HD_LED, XMOD LED

• extended Power Management

CPLD REV04 to REV05

• PS reboot via FSBL over MIO30 (need for proper PCI initialization on first power on without press Reset Button)
• SD Boot from micoSD only if switch S5-1/-2 is selected to ON
• RGPIO connection
• Add SD WP to FPGA
• Power, Rest Button debounced
• direct LED access via MIO and PL

Older Revision (PCB REV03) to CPLD REV04

• Bugfix: PCIe Reset Pin location.
• Bugfix: Swapping HDLED and PWRLED location.
• Bugfix: MEMS_CLKIN Pin location.
• Add XMOD 1 LED

Older Revision (PCB REV02) to CPLD REV04

• Add all functionality from older Revision (PCB REV03)