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Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD+Firmware

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Table of contents

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DateVersionChangesAuthor
2023-02-072.2
  • added column 'Firmware release' in 'Document Change History' table
  • changed template revision from list to table
ma
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  • Fix problem with pdf export and side scroll bar
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Overview

Firmware for PCB-Master CPLD with designator U17. Use first CPLD Device in Chain: LCMX02-1200HC.

Firmware for PCB-Slave CPLD with designator U39.  Use second CPLD Device in Chain: LCMX02-1200HC.

There are 3 different Firmware variants available:

  1. (Default): SCM_07A_default.jed/SCS_07A_default.jed
  2. (optional): SCM_07B_powerdown_disabled.jed/SCS_07B_powerdown_disabled.jed - Power down Sequencing is disabled (See Note Power Managment).
  3. (optional): SCM_07C_msdboot_disabled.jed/SCS_07C_msdboot_disabled.jed - CD Pin of MicroSD will not influence boot Mode (mircoSD can be used as Filesystem and system Boots from QSPI)

Feature Summary

  • Power Management (Slave CPLD)
  • Reset Management  (both)
    • SOM,USB,ETH,PCIE,ETH
  • CPLD JTAG (both)
  • FMC JTAG / PJTAG (Master CPLD)
  • FMC VADJ Power (Master CPLD)
  • Boot Mode (Slave CPLD)
  • PCIe (Slave CPLD)
  • SD  (both)
  • UART SoC (Slave CPLD)
  • UART (Debug) (Master CPLD)
  • CAN (Master CPLD)
  • USB (Master CPLD)
  • DisplayPort (Master CPLD)
  • SFP (Master CPLD)
  • I2C (Master CPLD)
  • LEDs (both)
  • RGPIO (both)


Firmware Revision and supported PCB Revision

See Document Change History

Product

...

Specification

Port Description

Light green rows are Master CPLD ports and light geen rows are Slave CPLD ports.

...

Name / opt. VHD NameDirectionPinPullup/PulldownBank PowerDescriptionCPLD

...

C_T1
24--3V3SB / currently_not_used U17

...

C_T2
26--3V3SB / currently_not_used U17

...

C_T3
25--3V3SB / currently_not_used U17

...

C_TCKin131None3V3SBJTAG J28 (XMOD2) / FMC JTAG
U17
C_TDIin136Up3V3SBJTAG J28 (XMOD2) / FMC JTAG
U17
C_TDO1 / C_TDOout137None3V3SBJTAG J28 (XMOD2) / FMC JTAG
U17
C_TMSin130None3V3SBJTAG J28 (XMOD2) / FMC JTAG
U17
CAN_FAULT
106Up3V3SBCANU17
CAN_RXin107Down3V3SBCANU17
CAN_Sout105None3V3SBCANU17
CAN_TXout104None3V3SBCANU17
CLK_125MHz / PHY_CLKin70Down1.8V / currently_not_used U17
CON_NTRST / JTAG_TRSTin117Up3V3SBJTAG, Connector J30U17
CON_RTCK / JTAG_RTCKout125None3V3SBJTAG, Connector J30U17
CON_sRST / JTAG_SRSTin127Up3V3SBJTAG, Connector J30U17
CON_TCK / JTAG_TCKin122Down3V3SBJTAG, Connector J30U17
CON_TDI / JTAG_TDIin119Down3V3SBJTAG, Connector J30U17
CON_TDO / JTAG_TDOout126None3V3SBJTAG, Connector J30U17
CON_TMS / JTAG_TMSin121Up3V3SBJTAG, Connector J30U17
DIR_T1
23--3V3SB / currently_not_used U17

...

DIR_T2
28--3V3SB / currently_not_used U17

...

DIR_T3
27--3V3SB / currently_not_used U17

...

DP_AUX_DE / DP_DEout92None3V3SBDisplay PortU17
DP_AUX_RX / DP_RXin91Up3V3SBDisplay PortU17
DP_AUX_TX / DP_TXout93None3V3SBDisplay PortU17
DP_ENout77None3V3SBDisplay PortU17
DP_TX_HPD / DP_HPDin94Up3V3SBDisplay PortU17
ETH_RSTout62None1.8VETH ResetU17
EX_IO1
112--3V3SB / currently_not_used U17
EX_IO2
113

...

--3V3SB / currently_not_used U17
EX_IO3
114--3V3SB / currently_not_used U17
EX_IO4
115--3V3SB / currently_not_used U17
F2_EN
19--3V3SB / currently_not_used U17

...

F2PWM
20--3V3SB / currently_not_used U17

...

F2SENSE
21--3V3SB / currently_not_used U17

...

FMC_CLK_DIR / FMC_CLKDIRin73None3V3SBFMCU17
FMC_TCKout95None3V3SBFMCU17
FMC_TDIout96None3V3SBFMCU17
FMC_TDOin97Down3V3SBFMCU17
FMC_TMSout98None3V3SBFMCU17
FMC_VID0out139Down3V3SBFMCU17
FMC_VID1out140Up3V3SBFMCU17
FMC_VID2out141Down3V3SBFMCU17
GND
84--3V3SBREV03 unconnected / currently_not_usedU17

...

HDIO_SC10 / SC10out60Down1.8VFPGA / DP_RX or 'Z'U17
HDIO_SC11 / SC11in59Down1.8VFPGA / DP_DEU17
HDIO_SC12 / SC12out58None1.8VFPGA / DP_HPDU17
HDIO_SC13 / SC13out57None1.8VFPGA / RGPIO TXU17
HDIO_SC14 / SC14in56None1.8VFPGA / RGPIO RXU17
HDIO_SC15 / SC15in55Up1.8VFPGA / RGPIO CLKU17
HDIO_SC16 / SC16in54Down1.8VFPGA / CAN_SU17
HDIO_SC17 / SC17in52Up1.8VFPGA / XMOD LED U17
HDIO_SC18 / SC18in68Down1.8VFPGA / CAN_TXU17
HDIO_SC19 / SC19out69None1.8VFPGA / CAN_RXU17
I2C_RSTout61None1.8VI2CU17
JTAGENB
120--3V3SBexternal Pin for CPLD Firmware Update U17
LED_1A / JLED1out109None3V3SBUSB3.0 LED JellowU17
LED_2A / JLED2Aout111None3V3SBUSB3.0 LED Green/OrangeU17
LED_2B / JLED2Bout110None3V3SBUSB3.0 LED Green/OrangeU17
MIO26out41Down1.8VMIO / PJTAGU17
MIO27out40Down1.8VMIO / PJTAGU17
MIO28in39Down1.8VMIO / PJTAGU17
MIO29out38Down1.8VMIO / PJTAGU17
OCLK_EN / OSC_ENout74None3V3SBProgrammable Oscillator U45U17
PHY_CONFIGout65None1.8VETH PHYU17
PHY_LED0in67

...

Down1.8VETH PHYU17
PHY_LED1in86Down3V3SBETH PHYU17
PHY_LED2in85Down3V3SBETH PHYU17
SC_CLK0 / CLK0in76Down3V3SB/ currently_not_usedU17
SC_CLK1 / CLK1in75Down3V3SB/ currently_not_usedU17
SC_IO0 / X0out50None1.8VMTS dummyU17
SC_IO1 / X1in49Up1.8Vinternal cpld RGPIO CLKU17
SC_IO2 / X2out48None1.8Vinternal cpld RGPIO TXU17
SC_IO3 / X3in47Down1.8Vinternal cpld RGPIO RXU17
SC_IO4 / X4out45None1.8VSD WP to slave cpldU17
SC_IO5 / X5in44--1.8VSTM dummyU17
SC_IO6 / X6

...

in43Up1.8V

...

internal ETH Reset from Slave to Master CPLDU17
SC_IO7 / X7out42None1.8V/ currently_not_usedU17
SC_IO8 / X8in22--3V3SBinternal cpld RGPIO available(1.8V on)U17
SC_SCL / SCLin14Up3V3SBI2C Mux U27 / currently_not_usedU17
SC_SDA / SDAin13Up3V3SBI2C Mux U27 / currently_not_usedU17
SC2_SW3 / SW3in6Up3V3SBDIP-Switch S5-3U17
SC2_SW4 / SW4in5Up3V3SBDIP-Switch S5-4U17
SD_WPin100Up3V3SBMMC SDWPU17
SFP_LED1 / SFP_LED0out81None3V3SBSFPU17
SFP_LED2 / SFP_LED1out82None3V3SBSFPU17
SFP_LED3 / SFP_LED2out78None3V3SBSFPU17
SFP_LED4 / SFP_LED3out83None3V3SBSFPU17
SFP1_LOS
32--3V3SBSFP / currently_not_used U17
SFP1_TX_DISout33None3V3SBSFPU17
SFP2_LOS
35--3V3SBSFP / currently_not_used U17
SFP2_TX_DISout34None3V3SBSFPU17
STAT_LED0 / LED0out99None3V3SBLED D4 Green U17
STAT_LED1 / LED1out128None3V3SBLED D1 Red U17
USB0_RST / USB_

...

RST
71None1.8VUSB (U9) PHY ResetU17
USBH_LED_G3
11--3V3SBUSB Hub (U4)  / currently_not_used U17
USBH_LED_G4
12--3V3SBUSB Hub (U4)  / currently_not_used U17
USBH_LED_SS1
9--3V3SBUSB Hub (U4)  / currently_not_used U17
USBH_LED_SS2
133--3V3SBUSB Hub (U4)  / currently_not_used U17
USBH_LED_SS3
132

...

--3V3SBUSB Hub (U4)  / currently_not_used U17
USBH_LED_SS4
138--3V3SBUSB Hub (U4)  / currently_not_used U17
USBH_MODE0out142None3V3SBUSB Hub (U4)U17
USBH_MODE1out143None3V3SBUSB Hub (U4)U17
USBH_RSTout10None3V3SBUSB Hub (U4)U17
XMOD1_A / XMOD_TXDout3Up3V3SBJ28 (XMOD 2 UART)U17
XMOD1_B / XMOD_RXDin2Up3V3SBJ28 (XMOD 2 UART)U17
XMOD1_E / XMOD_Eout4None3V3SBJ28 (XMOD 2 LED)U17
XMOD1_G / XMOD_Gout1Up3V3SBJ28 (XMOD 2 Button)U17
1.8V_EN / EN_1V8out106None3V3SBEnable 1.8V PowerU39
5V_EN / EN_5Vout115Up3V3SBEnable 5V Power, can be permanently enabled by S4-4U39
C_TCK
131--3V3SBJTAG J28 (XMOD2)  / currently_not_used U39
C_TDOout137None3V3SBJTAG J28 (XMOD2)
U39
C_TDO1 / C_TDIin136Up3V3SBJTAG J28 (XMOD2) U39
C_TMS
130--3V3SBJTAG J28 (XMOD2)  / currently_not_used U39
CLK_A / AUD_CLKout1Down1.8VAUDIO U3 CLKU39
CLK_CPLD / MEMS_CLKINin128None3V3SBU25 24,576MHzU39
DONEin67Up1.8VPS DoneU39
EN_DDRout86None3V3SBEnable Module DDR PowerU39
EN_FMC / FMC_ENout104None3V3SBFMCU39
EN_FPDout81None3V3SBEnable Module PS FPD PowerU39
EN_GT_Lout77None3V3SBEnable Module GT PowerU39
EN_GT_Rout93None3V3SBEnable Module GT PowerU39
EN_LPDout84None3V3SBEnable Module  PS LPD PowerU39
EN_PLout95None3V3SBEnable Module PL PowerU39
EN_PLL_PWRout78None3V3SBEnable Module SI5345 PowerU39
EN_PSGT / EN_PSGTRout75None3V3SBEnable Module PS GT PowerU39
ERR_OUT / ERRORin70Up1.8VModule PS Error Out / StatusU39
ERR_STATUS / ERR_STATin69Up1.8VModule PS Error StatusU39
F1PWMout121None3V3SBFAN1U39
F1SENSEin125Up3V3SBFAN1U39
FAN_FMC_EN / FMC_FAN_EN
132None3V3SBFMC FANU39
FMC_PG_C2Mout141Up3V3SBFMC PGU39
HD_LED_N / HDLED_Nout112None3V3SBJ10 HD LEDU39
HD_LED_P / HDLED_Pout110None3V3SBJ10 HD LEDU39
HDIO_SC0 / SC0in32Down1.8VFPGA IO /  forward to HD_LED_P / HDLED_PU39
HDIO_SC1 / SC1in33Down1.8V/ currently_not_used U39
HDIO_SC2 / SC2in34Down1.8V/ currently_not_used U39
HDIO_SC3
35--1.8V / currently_not_used U39
HDIO_SC4
25--1.8V / currently_not_used U39
HDIO_SC5 / SC5out26None1.8VFPGA IO / RGPIOU39
HDIO_SC6 / SC6in27Up1.8VFPGA IO / RGPIO CLKU39
HDIO_SC7 / SC7in28Down1.8V.FPGA IO / RGPIOU39
I2C_SCL / SCLin50Up1.8VI2C / currently_not_usedU39
I2C_SDA / SDAin52

...

Up1.8VI2C / currently_not_usedU39
INIT_B / INITin68Up1.8VModule PS Init_BU39
JTAGENB
120--3V3SBexternal Pin for CPLD Firmware UpdateU39
LP_GOOD / PG_LPDin83Up3V3SBModule LP Power GoodU39
MIO24
38Up1.8VMIO  / currently_not_used U39
MIO25
39--1.8VMIO  / currently_not_used U39
MIO30in48None1.8VMIO / USB ResetU39
MIO31in49None1.8VMIO / PCIe ResetU39
MIO32
40--1.8VMIO / currently_not_used U39
MIO33
41--1.8VMIO  / currently_not_used U39
MIO34
42--1.8VMIO  / currently_not_used U39
MIO35
43--1.8VMIO  / currently_not_used U39
MIO36
44--1.8VMIO  / currently_not_used U39
MIO37
45--1.8VMIO  / currently_not_used U39
MIO40in54Up1.8VMIOU39
MIO41
55--1.8VMIO  / currently_not_used U39
MIO42out60None1.8VMIOU39
MIO43in61Up1.8VMIOU39
MIO44
47None1.8VMIOU39
MOD_ENout119None3V3SBEnable Main Module Power 3.3VU39
MODE0out6None1.8VModule Boot ModeU39
MODE1out9None1.8VModule Boot ModeU39
MODE2out10None1.8VModule Boot ModeU39
MODE3out11None1.8VModule Boot ModeU39
MR / MRESETnout92None3V3SBModule PS Power ResetU39
PCI_SFP_ENout76None3V3SBSFPU39
PER_ENout117None3V3SBEnable 3.3V powerU39
PERST / PERSTnout139None3V3SBPCIE ResetnU39
PG_DDRin91Up3V3SBModule Power GoodU39
PG_FPDin85Up3V3SBModule Power GoodU39
PG_GT_Lin96Up3V3SBModule Power GoodU39
PG_GT_Rin94Up3V3SBModule Power GoodU39
PG_PLin82Up3V3SBModule Power GoodU39
PG_PLL_1V8 / PG_PLLin73Up3V3SBModule Power GoodU39
PG_PSGTin74Up3V3SBModule Power GoodU39
PLL_LOLn / PLL_LOLin58Up1.8VModule PLL / currently_not_usedU39
PLL_RST / PLL_RSTnout56None1.8VModule PLL ResetU39
PLL_SEL0out57None1.8VModule PLLU39
PLL_SEL1out59None1.8VModule PLLU39
POK_1V8in107Up3V3SBCarrier Power GoodU39
POK_FMCin99Up3V3SBFMC Power GoodU39
PROG_BOUT71Up1.8VModule PS_PROG_BU39
PSONout105None3V3SBATX J20 PS_ON_NU39
PWR_BTNin113Up3V3SBPower Button S1 or J10U39
PWRLED_N / LED_Nout111None3V3SBJ10 PWRU39
PWRLED_P / LED_Pout109None3V3SBJ10 PWRU39
PWROKin100Up3V3SBATX J20 PWROKU39
RST_BTNin114Up3V3SBReset Button S2 or J10U39
S_1
127--3V3SBBEEPER / currently_not_used U39
SC_IO0 / X0in12None1.8VMTS dummyU39
SC_IO1 / X1out13None1.8Vinternal cpld RGPIO CLKU39
SC_IO2 / X2in14None1.8Vinternal cpld RGPIO RXU39
SC_IO3 / X3out20None1.8Vinternal cpld RGPIO TXU39
SC_IO4 / X4in21Up1.8VMMC SD WP from masterU39
SC_IO5 / X5out22None1.8VSTM dummyU39
SC_IO6 / X6

...

out23None1.8V

...

internal ETH Reset from Slave to Master CPLDU39
SC_IO7 / X7in24Down1.8V / currently_not_used U39
SC_IO8 / X8out126Down3V3SBinternal cpld RGPIO available(1.8V on)U39
SC2_SW1 / SW1in133Up3V3SBS5-1 / Boot Mode SelectionU39
SC2_SW2 / SW2in138Up3V3SBS5-2 / Boot Mode SelectionU39
SD_A_ENout140None3V3SBMicro SDU39
SD_B_ENout122None3V3SBMMC SDU39
SD_CD / SD_CD_OUTout65None1.8VSD Card detect to FPGAU39
SD_CD_Bin143Up3V3SBMMC SD CDU39
SD_CD_Sin142Up3V3SBMicro SD CDU39
SEL_SD / SD_SELout62None1.8VSD select (Mirco or MMC)U39
SRST_B / SRSTnout19None1.8VModule PS_SRST_BU39
STAT_LED2 / LED2out98None3V3SBLED D6 GreenU39
STAT_LED3 / LED3out97None3V3SBLED D7 RedU39
XMOD2_A / XMOD_TXDout5None1.8VJ12 (XMOD 1 UART)U39
XMOD2_B / XMOD_RXDin4Up1.8VJ12 (XMOD 1 UART)U39
XMOD2_E / XMOD_LEDout3Down1.8VJ12 (XMOD 1 LED)U39
XMOD2_G / XMOD_BTNin2Up1.8VJ12 (XMOD 1 Button)U39

Functional Description

JTAG

JTAGENB set carrier board CPLD into the chain for firmware update. For Update set DIP S4-3 to ON.

Power

FMC VADJ is handled on master CPLD.

DIPPositonDescription
S5-4ON1.8V
S5-4OFF1.2V

Power on and off sequencing is done with slave CPLD.

Scroll Title
anchorFigure_power
titlePower On/OFF Sequencing

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision

...

4
diagramNamepower_seq
simpleViewertrue
width1200
linksauto
tbstyletop
diagramWidth2170
height

...

1986

Note: Power downs sequencing above can be disabled with second optional CPLD Firmware:

  1. Configure Firmware version SCM_07B_powerdown_disabled.jed/SCS_07B_powerdown_disabled.jed
  2. Add Jumper to J10-6 and J10-8 instead of Enclousure Button
  3. Module will be powered and boot on with Main power supply.

Reset

Power, Zynq reset and PCIe is handle on Slave CPLD

USB, ETH, I2C Reset is handled on Master CPLD

Type controlled by
PCiePower On Reset_N(pwr_rdy), MIO31
USB(PHY+HUB)Power On Reset_N(pwr_rdy), MIO30
Modul PLLPower On Reset_N(pwr_rdy)
PS_POR_BReset Button (hold long time ~3s), zynq_reset_ready
PS_SRST_BReset Button (hold short time ~1s), zynq_reset_ready
FMC_FAN_ENPower On Reset_N(pwr_rdy)
I2C_RSTPower On Reset_N(pwr_rdy)
ETH_RSTPower On Reset_N(pwr_rdy), MIO24


JTAG

CPLD JTAG only needed for CPLD Firmware update.

FMC and CPLD JTAG is accessable over XMOD2(J28).

S4-3
ONCPLD Access on both CPLD
OFFFMC JTAG Access

PJTAG on connector J17 is routed over Master CPLD to MIO26..29.

SignalConnection
JTAG_TCKMIO26
JTAG_RTCKJTAG_TCK
JTAG_TDIMIO27
JTAG_TDOMIO28
JTAG_TMSMIO29
JTAG_SRSTnot usedconnected only to FPGA RGPIO
JTAG_TRSTnot used, connected only to FPGA RGPIO

Boot Mode

Boot Mode is handled on Slave CPLD.

S5-1S5-2Description
ONONDefault, boot from SD/microSD or SPI Flash if no SD is detected
OFFONBoot from eMMC
ONOFFBoot mode PJTAG0
OFFOFFBoot mode main JTAG

Note: There is a second CPLD Variant available, where microSD will not change the boot mode.

  1. Configure Firmware version SCM_07C_msdboot_disabled.jed/SCS_07C_msdboot_disabled.jed
  2. Boot mode will be still QSPI,when microSD is insered.

PCIe

PCIe is handled on Slave CPLD.

SignalConnection
PERSTnPower On reset and MIO31

SD

SD is mainly handled on Slave CPLD

SD SignalDescription
SD_SELCD Pin form microSD selects the SD Card, microSD has higher priority
CD (MIO45)mircoSD and SD Card detect
WP(MIO44)0 when miroSD is used else SD card detect (forrward over Master CPLD)

UART SoC

SoC(ZynqMP) is accessible over XMOD1(J12) and connected to ZynqMP over Slave CPLD

SignalDescription
XMOD_TXDZynqMP TX(MIO43), when PWR Ready else 1
XMOD_RXDto ZynqMP RX(MIO42), when PWR Ready else 1

UART (Debug)

Simple Firmware Debug UART is accessible over XMOD2(28) over Master CPLD

Firmware Versions and some statistics can be displayed over second XMOD:

  • Included since CPLD Firmware Update to REV07
  • UART Speed is 115200
  • Press XMOD Button to see output, otherwise RX/TX are loop backed
SignalDescription
XMOD_TXDDebug output, when XMOD Button is pressed else RX loopback
XMOD_RXDDebug input(currently no function), when XMOD Button is pressed else TX loopback

CAN

CAN  is handled mainly on Master CPLD

SignalDescription
CAN_TXSC18(FPGA LOC depends on module)
CAN_RXSC19(FPGA LOC depends on module)
CAN_SSC16(FPGA LOC depends on module)
CAN_FAULTMonitoring over RGPIO only

USB

USB Reset is handled mainly on Master CPLD

SignalDescription
USB_RSTPower On Reset_N and MIO30 (over slave CPLD)
USBH_RSTPower On Reset_N and MIO30 (over slave CPLD)
USBH_MODE0const 1
USBH_MODE1const 1

DisplayPort

DisplayPort is handled on Master CPLD

SignalDescription
DP_EN

...

Power On Reset_N
DP_RXto SC10 when SC11 is 0 else Z
DP_TXSX10
DP_DESC11
DP_HPDSC12

SFP

ETH Reset is handled on Master CPLD

SignalDescription
SFP1_TX_DISconst 0 (Enabled)
SFP2_TX_DISconst 0 (Enabled)

I2C

I2C MUX is handled on Master CPLD

SignalDescription
I2C_RSTPower On Reset_N

ETH

ETH Reset is handled on Master CPLD

SignalDescription
ETH_RSTPower On Reset_N and MIO24 (over slave CPLD)
PHY_CONFIGconst 1

LEDs

LEDs are handled on both CPLDs.

They used different Blink Sequence to indicate all state:

******** (slow blinking)~0,7 Hzcontinuous blinking, like SFP LEDs or Enclosure HD LED when board is powered down
******** (fast blinking)~5,8 Hzcontinuous blinking, like D6 LED or Enclosure Power LED when board is powered down
*****ooo~0,7 Hz, duty cycle 5/85 times fast blink with a break
****oooo~0,7 Hz, duty cycle 4/84 times fast blink with a break
***ooooo~0,7 Hz, duty cycle 3/83 times fast blink with a break
**oooooo~0,7 Hz, duty cycle 2/82 times fast blink with a break
*ooooooo~0,7 Hz, duty cycle 1/81 times fast blink with a break
ON---LED ON
OFF---LED OFF


DesignatorColorUsageDescription
D7Redstatus


PriorityDescriptionBlink sequencing
1PS POR Reset pressed long time (or whole system is powered off)ON
2PS Soft Reset pressed short timeOFF
3SD Boot*ooooooo
4QSPI Boot**oooooo
5eMMC Boot***ooooo
6PJTAG Boot****oooo
7JTAG Boot*****ooo
8Error******** (fast blinking)


D6Greenstatus


PriorityDescriptionBlink sequencing
1Power OFF******** (fast blinking)
2PG_LPD low*****ooo
3PG_FPD low****oooo
4PG_PL low***ooooo
5PG_DDR low or PG_PSGT low or PG_PLL low or PG_GT_L low or PG_GT_R low**oooooo
6POK_1V8 low or POK_FMC low or perihpery_pg low or (Main Power State Machine Ready and FMC Sanity check low)*ooooooo
7Main Power State Machine ReadyOFF
8ERROR some power failed, see XMOD LEDsON


J10 Power LEDBlue (symbol light bulb)status/user


PriorityDescriptionBlink sequencing
1power button pressed long time forced power down******** (fast blinking)
2

Main Power State Machine Idle and Power of State is off

******** (slow blinking)
3power button pressed short time power to power on/off*****ooo
4PS reset button pressed long time****oooo
5PS reset button pressed short time***ooooo
6power down sequencing is running**oooooo
7whole system hold into reset*ooooooo
8MIO40User Defined


J10 HD LED

Red (symbol drive)

status/user


PriorityDescriptionBlink sequencing
1PS Init is low******** (fast blinking)
2PS Error High*****ooo
3PS Error Status High****oooo
4SOC Done  low***ooooo
5SC0User Defined


XMOD1 D4Redstatus


PriorityXMOD ButtonDescriptionBlink sequencing
1Pressedpower button pressed long time forced power down******** (fast blinking)
2PressedMain Power State Machine Idle and Power of State is power down
sequencing		*****ooo
3Pressed

PS reset button pressed

****oooo
4PressedPower button pressed short time power on/off***ooooo
5PressedPower of State is power down sequencing**oooooo
6PressedSystem hold into reset*ooooooo
7PressedPS Init lowON
1UnpressedProblem with other CPLD, FMC is disabled******** (fast blinking)
2UnpressedMain Power State Machine Wait Ready ON/OFF*****ooo
3UnpressedMain Power State Machine 3.3V and VADJ ON/OFF****oooo
4Unpressedpower not ready (power reset)**oooooo
5Unpressedzynq reset*ooooooo
7UnpressedPS Init lowON
xPressed/Unpressedall fineOFF


XMOD2 D4Redstatus/user


PriorityDescriptionBlink sequencing
1Power On Reset********  (slow blinking)
2PS Init low******** (fast blinking)
3SC17User Defined


SFP D1Redstatus/user


PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3RGPIO(0), when RGPIO Enabled over FPGAUser Defined
4--OFF


SFP D8Greenstatus/user


PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3RGPIO(1), when RGPIO Enabled over FPGAUser Defined
4--OFF


D17 - USB HUB LED (Suspend)GreenstatusON, no USB connected, OFF, USB connected
SFP D9Redstatus/user


PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3RGPIO(2), when RGPIO Enabled over FPGAUser Defined
4--OFF


SFP D10Greenstatus/user


PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3RGPIO(3), when RGPIO Enabled over FPGAUser Defined
4--OFF


ETH J7Yellowstatus


PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3ETH PHY LED(not PHY_LED0)


ETH J7Green/Orangestatus


PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3ETH PHY LED(PHY_LED1)


D4Greenstatus/user


PriorityDescriptionBlink sequencing
11.8V disabled, inter CPLD RGPIO is disabled******** (fast blinking)
21.8V enabled, inter CPLD RGPIO is disabled*****ooo
3Power On Reset****oooo
4USB Reset***ooooo
5RGPIO(4), when RGPIO Enabled over FPGAUser Defined
6all fine*ooooooo


D5Redstatus/user


PriorityDescriptionBlink sequencing
11.8V disabled, inter CPLD RGPIO is disabled******** (fast blinking)
21.8V enabled, inter CPLD RGPIO is disabled*****ooo
3Power On Reset****oooo
4PCie Reset***ooooo
5RGPIO(4), when RGPIO Enabled over FPGAUser Defined
6all fine*ooooooo



RGPIO 

There are 3 RGPIO interfaces, one InterCPLD RGPIO, and one from every CPLD to SoC.

InterCPLD RGPIO handles:

SignalDescription
Reset Button (SW)for monitoring only
PS PORfor monitoring only
PS ERR Statfor monitoring only
PS ERRfor monitoring only
PS Initfor monitoring only
PCIe Resetfor monitoring only
USB Resetfor USB Reset and monitoring
Power On Resetfor Power On Reset and monitoring
inter FPGAData from Slave RGPIO to Master RGPIO (for test only)


Master CPLD-SoC RGPIO (accesseble via SoC):

SignalDescription
FPGA Read (23)JTAG_SRST
FPGA Read (22)JTAG_TRST
FPGA Read (21)FMC_CLKDIR
FPGA Read (20)SD_WP
FPGA Read (19)unused 0
FPGA Read (18)SW4
FPGA Read (17)SW3
FPGA Read (16)XMOD_G
FPGA Read (15 dt 13)PHY LEDs
FPGA Read (12)CAN_FAULT
FPGA Read (11 dt 8)current RGPIO Mux
FPGA Read (7 dt 0)

Data depends on MUX:

0Data(7dt0) from Slave CPLD-SoC RGPIO
1POR Statistic
2PS RST Statistic
3PS POR Statistic
4PS Init Statistic
5PS ERR Statistic
6PS ERR Stat Statistic
7PCie RST Statistic
8USB RST Statistic


FPGA Write (23 dt 12)unused
FPGA Write (11 dt 8)RGPIO Mux, see FPGA Read (7 dt 0) , when RGIO active
FPGA Write (7 dt 6)unused
FPGA Write (5 dt 0)Diverse LED controll(see LED description) , when RGIO active

Slave CPLD-SoC RGPIO (accesseble via SoC):

SignalDescription
FPGA Read (23)PLL_LOL
FPGA Read (22)PG_PLL
FPGA Read (21)PG_PL
FPGA Read (20)PWROK and pwrok_force_zero_n
FPGA Read (19)fmc_sanity_check
FPGA Read (18)POK_FMC
FPGA Read (17)PG_GT_R
FPGA Read (16)PG_GT_L
FPGA Read (15)PG_PSGT
FPGA Read (14)PG_FPD
FPGA Read (13)PG_DDR
FPGA Read (12)PG_LPD
FPGA Read (11 dt 8)current Boot Mode
FPGA Read (7)ERR_STAT
FPGA Read (6)ERROR
FPGA Read (5)SD_CD_B
FPGA Read (4)SD_CD_S
FPGA Read (3)unused const 1
FPGA Read (2)XMOD_BTN
FPGA Read (1)SW2
FPGA Read (0)SW1
FPGA Write (23 dt 8)unused
FPGA Write (7dt 0)Readable over Master CPLD-SoC RGPIO, when RGIO active

Appx. A: Change History and Legal Notices

Revision Changes

MasterSlave

CPLD REV07 to REV08

  • add major and minor revision number to uart string
  • bugfix DP_EN  inverted
  • reduce statistic cnt size to save resources for newer diamond version
  • add X6 as optional ETH Reset from SOM(over MIO24 from Slave CPLD)

CPLD REV06 to REV07

  • complete rework

  • add inter CPLD RGPIO

  • new LED debugging sequencing

  • simple UART output with Revision Number and some statistic on second XMOD

CPLD REV05 to REV06

  • BUGFIX: renamed SC19 to SC17
  • Connect FMC JTAG to XMOD2 JTAG
  • Connect PJTAG0 (MIO29..26) to JTAG Pin Header J30
  • Connect CAN to PL
  • RGPIO Pin changes

CPLD REV04 to REV05

  • SD WP
  • XMOD LED access over PL

Older Revision (PCB REV03) to CPLD REV04

  • Fix USB HUB Mode default state over RGPIO
  • Invert JLED2B over RGPIO

Older Revision (PCB REV02) to CPLD REV04

  • Add all functionality from older Revision (PCB REV03)

CPLD REV07 to REV08

  • PSON inverted
  • Add MIO24 as additional ETH reset from SoM, and use X6 to forward it to Master CPLD
  • remove unused aud_clk_c constrain

CPLD REV06 to REV07

  • complete rework
  • add variants (power up and SD)multi-functions for buttons
  • power on and power downs sequencing
    • module complete disable on power down
    • power on sequencing
    • power down sequencing --> can be forced with power button (hold longer)
  • Soft PS or PS POR Reset on Reset button (hold longer for PS POR Reset)
  • add inter CPLD RGPIO
  • new SoC RGPIO Pinout
  • removed reboot for pcie initialization
  • new LED debugging sequencing
  • Disabled UART on power down state
  • bugfix WP pin for microSD slot
  • removed PCIe Reboot.

CPLD REV05 to REV06

  • LED Status changes of LED D2 D3 and HD_LED, XMOD LED

  • extended Power Management

CPLD REV04 to REV05

  • PS reboot via FSBL over MIO30 (need for proper PCI initialization on first power on without press Reset Button)
  • SD Boot from micoSD only if switch S5-1/-2 is selected to ON
  • RGPIO connection
  • Add SD WP to FPGA
  • Power, Rest Button debounced
  • direct LED access via MIO and PL

Older Revision (PCB REV03) to CPLD REV04

  • Bugfix: PCIe Reset Pin location.
  • Bugfix: Swapping HDLED and PWRLED location.
  • Bugfix: MEMS_CLKIN Pin location.
  • Add XMOD 1 LED

Older Revision (PCB REV02) to CPLD REV04

  • Add all functionality from older Revision (PCB REV03)

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescriptionFirmware Release

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REV08REV05

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  • Document Style Update
  • REV08
2024-10-30

2019-05-06

...


v.13

REV07REV03,REV04*

 

  • REV07 finished
  • *please write to Trenz Electronic support for PCB REV02

...

v.1

...

2019-05-06

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