Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Scroll Title
anchorTable_OBP
titleOn board peripherals

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Chip/InterfaceDesignatorNotes
SDRAMU2
FTDI FT2232HU3JTAG/UART Adapter
SPI Flash MemoryU5
EEPROMU9
OscillatorU712MHz clock source
A2D ConvertorU12, U14Analog to Digital Convertor
8x User LEDsD2...9Red LEDs


Quad SPI Flash Memory

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

Page properties
hiddentrue
idComments

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

...

Notes
Scroll Title
anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

-
Data input/output

DQ0 ... DQ15

bank 6

-
Data mask

DQM0 ... DQM1

bank 6

-
ClockCLKbank 3
Control Signals

CS

bank 3

Chip select

CKE

bank 3

Clock enable

RAS

bank 3

Row Address Strobe

CAS

bank 3

Column Address Strobe

WEbank 3Write Enable
MIO PinSchematicU?? Pin




RTC

Scroll Title
anchorTable_OBP_RTC
titleI2C interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO PinSchematicU? PinNotes









...