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Scroll Title |
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anchor | Table_OBP |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Notes |
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SDRAM | U2 |
| FTDI FT2232H | U3 | JTAG/UART Adapter | SPI Flash Memory | U5 |
| EEPROM | U9 |
| Oscillator | U7 | 12MHz clock source | A2D Convertor | U12, U14 | Analog to Digital Convertor | 8x User LEDs | D2...9 | Red LEDs |
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Quad SPI Flash Memory
TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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Scroll Title |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
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Address inputs | A0 ... A13 | bank 3 | - | Bank address inputs
| BA0 / BA1 | bank 3 | - | Data input/output | DQ0 ... DQ15 | bank 6 | - | Data mask | DQM0 ... DQM1 | bank 6 | - | Clock | CLK | bank 3 |
| Control Signals | CS | bank 3 | Chip select | CKE | bank 3 | Clock enable | RAS | bank 3 | Row Address Strobe | CAS | bank 3 | Column Address Strobe | WE | bank 3 | Write Enable |
MIO Pin | Schematic | U?? Pin | Notes
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RTC
Scroll Title |
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anchor | Table_OBP_RTC |
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title | I2C interface MIOs and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Schematic | U? Pin | Notes |
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