Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
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Pin 12, ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface | Pin 13, ADBUS1ADBUS1 | TDI | FPGA bank 1B, pin F5 | Pin 14, ADBUS2ADBUS2 | TDO | FPGA bank 1B, pin F6 | Pin 15, ADBUS3ADBUS3 | TMS | FPGA bank 1B, pin G1 | Pin 32, BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user configurable | Pin 33, BDBUS1BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | user configurable | Pin 34, BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user configurable | Pin 35, BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user configurable | Pin 37, BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | user configurable | Pin 38, BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user configurable |
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