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Signals, Interfaces and Pins

I/O Signals

List Overview of the PS/PL banks I/O signals between PS/PL banks and connected to the external connectors:

Table x2: .

JTAG Interface

JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through FTDI USB/UART FIFO bridge connected to the J9 Micro USB connector.

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Table x3: Quad SPI interface signals and connections.

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Table 4: .

USB Interface

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Power and Power-On Sequence

Power Supply

Single 5V power supply with minimum power can be supplied by the external power supply through connector J12 or via USB connection to the host system through USB connector J8 or J9. Minimum current capability of 2A for system startup 1A for external power supply is recommended.

Power Consumption

TBD - To Be DeterminedPower consumption is to be determined by the user and depends on SoC's FPGA design and connected hardware.

Power-On Sequence

There is no specific power-on sequence, system will power-up itself if 5V is present either from through J8, J9 or J12.

Variants Currently in Production

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