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List of signals between PS/PL banks and external connectors:
| Bank | Type | Connector | I/O Signal Count | Voltage | Notes |
|---|---|---|---|---|---|
| 34 | HR | J1 | 6 | 3.3 | D8 .. 13, SDA, SCL |
| 34 | HR | J2 | 8 | 3.3 | D2 .. 7, RXD, TXD |
| 34 | HR | J6 | 8 | 3.3 | PIO01 .. PIO08 |
| 35 | HR | J4 | 7 | 3.3 | AIN0 .. 5 |
| 35 |
| HR | J5 | 1 | 3.3 | ESP_GPIO2 | |
| 500 | MIO | J10 | 6 | 3.3 | SDCARD |
| 501 | MIO | J5 | 4 | 3.3 | ESP_RXD, ESP_TXD, ESP_GPIO0, MOD_RST |
JTAG Interface
JTAG access to the Xilinx ZYNQ XC7Z010 SoC is provided through testpoints TP1-T4.
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Overview
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