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Storage device name	IC	Content	Notes
Quad SPI Flash	U5	Empty	-
Configuration EEPROM	U6	Empty	Pre-Programmed	Xilinx License -

Table 1: Initial delivery state of programmable devices on the module

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Bank	Type	VCCIO	I/O Signal Count	Available on Connectors	Notes
34	HR	3.3V	44	24	8 user I/O's on Pmod connector J6, female pin header J1 and J2 each.
35	HR	3.3V	8	7	6 user I/O's on female pin header J4, 1 user I/O on female pin header J5.
500	PS MIO	3.3V	15	-	6 MIO - pins used for QSPI flash memory interface, 7 MIO - pins used for SD Card interface, 1 MIO-pin connected to red LED D2.
501	PS MIO	3.3V	16	4	12 MIO - pins used for USB ULPI interface, 4 MIO-pins used for ESP8266 interface header J5.
0	Config	3.3V	5	-	4 I/O's are dedicated to JTAG interface, 'PROG_B'-signal is connected to voltage monitor circuit 23.

Table 3: General overview of Zynq SoC PL/PS I/O banks

JTAG Interface

JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through FTDI USB/UART FIFO bridge connected to the Micro USB2 connector J9.

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bank

USB2 to JTAG/UART Adapter

The TE0723 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx Zynq XC7Z010 SoC. There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools.

Warning
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Channel A of the FTDI IC is configured as JTAG interface (MPSSE) connected to the JTAG interface of the Zynq SoC on configuration bank 0:

Zynq SoC U1	Signal Schematic Name	FT2232H IC U3 Pin

Zynq SoC U1

Note

Pin G9

TCK

12

G9-

L7

TDI

13

L7

L8

-

TDO

14

L8 -

L9

TMS

15

Pin L9 -

Table 4: JTAG interface signals

14 additional bus lines of Channel B of the FTDI IC can be used as UART interface routed to CPLD. Also 6 additional bus-lanes are connected to the System Controller CPLD and available for user-specific use.are routed to Zynq SoC PL bank 34 and are available to the user. The FTDI chip which converts signals from USB2 to a variety of standard serial and parallel interfaces like UART and user GPIO's in FIFO mode. Refer to the FTDI data sheet to get information about the capacity of the FT2232H IC.

Zynq SoC U1	Signal Schematic Name	FT2232H IC

U3Zynq SoC U1

Note

BDBUS0Pin 12Pin G9-TDIPin 13Pin L7-TDOPin 14Pin L8 -TMSPin 15Pin L9 -

U3 Pin
Bank 34, pin H13	BDBUS0	32
Bank 34, pin H14	BDBUS1	33
Bank 34, pin J15	BDBUS2	34
Bank 34, pin J14	BDBUS3	35
Bank 34, pin K15	BDBUS4	37
Bank 34, pin L15	BDBUS5	38
Bank 34, pin L14	BDBUS6	39
Bank 34, pin M15	BDBUS7	40
Bank 34, pin M14	BCBUS0	42
Bank 34, pin N14	BCBUS1	46
Bank 34, pin P15	BCBUS2	47
Bank 34, pin N13	BCBUS3	48
Bank 34, pin R15	BCBUS4	49
Bank 34, pin P14	BCBUS7	53

Table 5: FTDI FT2232H bus line Table 5: JTAG interface signals

Quad SPI Interface

Quad SPI Flash memory (U5) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

's

Zynq SoC	U1 Pin	Signal Schematic Name
Bank 500, pin MIO1	SPI0_CS	1
Bank 500, pin MIO2	SPI0_DQ0/MIO2	5
Bank 500, pin MIO3	SPI0_DQ1/MIO3	2
Bank 500, pin MIO4	SPI0_DQ2/MIO4	3
Bank 500, pin MIO5	SPI0_DQ3/MIO5	7
Bank 500, pin MIO6	SPI0_SCK	6

Table 46: Quad SPI interface signals and connections

SD Card Interface

TE0723 module has on-board 3.3V SD Card socket (J10) with card detect switch wired to the SoC PS MIO bank 500.

's Connected ToCard detect switchDAT0CMDCLKDAT1DAT3CD/DAT3

Zynq SoC	U1 Pin
Bank 500, pin MIO0	Card detect switch	J10-9
Bank 500, pin MIO10	DAT0	J10-7
Bank 500, pin MIO11	CMD	J10-3
Bank 500, pin MIO12	CLK	J10-5
Bank 500, pin MIO13	DAT1	J10-8
Bank 500, pin MIO14	DAT3	J10-1
Bank 500, pin MIO15	CD/DAT3	J10-2

Table 47: SD card Card socket signals

USB Interface

's U18-7U18-29U18-3U18-4U18-6U18-9U18-10

Zynq SoC	U1 Pin	Connected To	Signal Schematic Name
Bank 501, pin MIO28		OTG-DATA4	7
Bank 501, pin MIO29	U18-31	OTG-DIR	31
Bank 501, pin MIO30		OTG-STP	29
Bank 501, pin MIO31	U18-2	OTG-NXT	2
Bank 501, pin MIO32	MIO32	OTG-DATA0	3
Bank 501, pin MIO33		OTG-DATA1	4
Bank 501, pin MIO34	U18-5	OTG-DATA2	5
Bank 501, pin MIO35		OTG-DATA3	6
Bank 501, pin MIO36	U18-1	OTG-CLK	1
Bank 501, pin MIO37		OTG-DATA5	9
Bank 501, pin MIO38		OTG-DATA6	10
Bank 501, pin MIO39	U18-13	OTG-DATA7	13

Table 58: USB interface. signals

ESP Wi-Fi Interface

Interface for the ESP8266 Wi-Fi module is provided through connector J5.

Zynq SoC 's U1 Pin	Connected To	Signal Schematic Name	Connected to
Bank 501, pin MIO48	ESP_TXD	J5-2ESP_TXD
Bank 501, pin MIO49	ESP_RXD	J5-7ESP_RXD
Bank 501, pin MIO52	MOD_RST	J5-6	MOD_RST
Bank 501, pin MIO53	ESP_GPIO0	J5-3ESP_GPIO0
Bank 35, pin G15	ESP_GPIO2	J5-5	ESP_GPIO2

Table 6: ESP8266 Wi-Fi module interface.

I²C Interface

I²C interface pins SCL and SDA from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.

Zynq SoC 's U1 PinConnected To	Signal Schematic Name	Connected to
R13	SDA	J1-9SDA
P13P13	SCL	J1-10	SCL

Table 7: Zynq SoC I²C interface.

On-board Peripherals

DDR Memory

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