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I/O Signals
Overview of the Zynq SoC's PS/PL banks I/O signals connected to the external connectors:
| Bank | Type | Connector | Signal Count | Voltage | Notes |
|---|---|---|---|---|---|
| 34 | HR | J1 | 8 | 3.3V | D8 .. 13, SDA, SCL |
| 34 | HR | J2 | 8 | 3.3V | D2 .. 7, RXD, TXD |
| 34 | HR | J6 | 8 | 3.3V | PIO01 .. PIO08 |
| 35 | HR | J4 | 6 | 3.3V | AIN0 .. 5 |
| 35 | HR | J5 | 1 | 3.3V | ESP_GPIO2 |
| 500 | MIO | J10 | 7 | 3.3V | SDCARD |
| 501 | MIO | J5 | 4 | 3.3V | ESP_RXD, ESP_TXD, ESP_GPIO0, MOD_RST |
Table 2: Overview of the Zynq SoC's PS/PL banks I/O signals.
JTAG Interface
JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through FTDI USB/UART FIFO bridge connected to the J9 Micro USB connector.
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| Zynq SoC's Pin | Connected To | Signal Name |
|---|---|---|
| MIO28 | U18-7 | OTG-DATA4 |
| MIO29 | U18-31 | OTG-DIR |
| MIO30 | U18-29 | OTG-STP |
| MIO31 | U18-2 | OTG-NXT |
| MIO32 | U18-3 | OTG-DATA0 |
| MIO33 | U18-4 | OTG-DATA1 |
| MIO34 | U18-5 | OTG-DATA2 |
| MIO35 | U18-6 | OTG-DATA3 |
| MIO36 | U18-1 | OTG-CLK |
| MIO37 | U18-9 | OTG-DATA5 |
| MIO38 | U18-10 | OTG-DATA6 |
| MIO39 | U18-13 | OTG-DATA7 |
Table x5: USB interface.
ESP Wi-Fi Interface
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| Zynq SoC's Pin | Connected To | Signal Name |
|---|---|---|
| MIO48 | J5-2 | ESP_TXD |
| MIO49 | J5-7 | ESP_RXD |
| MIO52 | J5-6 | MOD_RST |
| MIO53 | J5-3 | ESP_GPIO0 |
Table x6: ESP8266 Wi-Fi module interface.
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I2C interface pins from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.
| Zynq SoC's Pin | Connected To | Signal Name |
|---|---|---|
| R13 | J1-9 | SDA |
| P13 | J1-10 | SCL |
Table x:7: Zynq SoC I2C interface.
On-board Peripherals
DDR Memory
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| Source | Signal | Frequency | Destination | Pin Name | Notes |
|---|---|---|---|---|---|
| U14 | PS_CLK | 52.000000 MHz | U1 | PS_CLK_500 | Zynq SoC PS subsystem main clock. |
| U14 | OTG-RCLK | 52.000000 MHz | U18 | REFCLK | USB3320C PHY reference clock. |
| U7 | OSCI | 12.000000 MHz | U3 | OSCI | FT2232H oscillator input. |
Table x8: Reference clock signals.
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| LED | Color | Connected To | Description and Notes |
|---|---|---|---|
| D2 | Red | MIO9, U1 | User LED. |
| D6 | Green | U1, bank 34 pin G14 | FPGA_LED |
| D7 | Green | 3.3V | PWR_LED, power-on LED. |
Table x9: On-board LEDs.
Power and Power-On Sequence
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| Module Variant | Xilinx Zynq SoC | DDR3L SDRAM | ARM Cores | PL Cells | LUTs | Flip-Flops | Block RAM | DSP Slices |
|---|---|---|---|---|---|---|---|---|
| TE0723-02 | XC7Z010-1CLG225C | 128 MBytes | Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 |
| TE0723-03M | XC7Z010-1CLG225C | 512 MBytes | Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 |
| TE0723-03-07S-1C | XC7Z007S-1CLG225C | 512 MBytes | Single-core | 23K | 14,4K | 28,8K | 1.8 MBytes | 66 |
Table 810: Module variants.
Technical Specifications
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Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
VIN supply voltage | -0.5 | 3.6 | V | Xilinx datasheet DS187. |
Storage temperature | -40 | +85 | °C |
Table x11: TE0723 module absolute maximum ratings.
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| Supply voltage | 1.14 | 3.465 | V | Xilinx datasheet DS187. |
Table x12: TE0723 module recommended operating conditions.
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
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| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| 2016-07-15 | 03 | Click to see PCN. | TE0723-03 | |
2015-11-06 | 02 | TE0723-02 | ||
01 |
|
Table x13: TE0723 hardware revision history.
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Date | Revision | Contributors | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Jan Kumann | Initial document. |
Table x14: Document change history.
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