Page History
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| Analog differential Input Pin Pair | Connector pin | Connector pinSignal Schematic Name | Note |
|---|---|---|---|
| IO_L1P_T0_AD0P_35, pin F12 IO_L1N_T0_AD0N_35, pin E13 | J4-3 J4-1 | AIN2 AIN0 | I/O's also usable in digital mode |
IO_L2P_T0_AD8P_35, pin F11 | J4-4 J4-2 | AIN3 AIN1 | I/O's also usable in digital mode |
IO_L3P_T0_DQS_AD1P_35, pin F13 | J4-6 J4-5 | AIN5 AIN4 | I/O's also usable in digital mode |
Table 12: Auxiliary Analog Inputs of the Zynq device
Note: These 6 auxiliary analog inputs pins are analog inputs are shared with PL bank pins and can be used as regular digital I/O's.
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| Board Variant | FPGA | Design | Typical Power, 25°C ambient |
|---|---|---|---|
| TE0723-02 | XC7Z010-1CLG225C | Not configured | TBD* |
| TE0723-03M | XC7Z010-1CLG225C | Not configured | TBD* |
| TE0723-03-07S-1C | XC7Z007S-1CLG225C | Not configured | TBD* |
Table 1516: Module power consumption
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The voltage direction of the power rails is directed at on-board connectors' view:
| Main Power Pins Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| J12 | 5V | In | 1 | 5V power supply pin header. |
| J3 | 3.3V | Out | 2, 4 | On-board 3.3V voltage level available. |
| 5V | In / Out | 5 | On-board 5.0V voltage level available or supply pin. |
Table 2017: Main power pin header description
| I/O pin header | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| J5 | 3.3V | Out | 4, 8 | I/O header VCCIO. |
| J6 | 3.3V | Out | 6, 12 | I/O header VCCIO. |
Table 2018: Power pin description of I/O pin header
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| Peripheral Socket Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| J8 / J9 | USB-VBUS | In / Out | 1 | Direction depends on USB2 mode. |
| J10 | 3.3V | Out | 4 | MikroSD Card socket VDD. |
Table 2219: Power pin description of peripheral connector
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Bank | Bank I/O Voltage VCCO | Voltage Range |
|---|---|---|
| 0 (config) | 3.3V | fixed |
| 500 (MIO) | 3.3V | fixed |
| 501 (MIO) | 3.3V | fixed |
| 34 (HR) | 3.3V | fixed |
| 35 (HR) | 3.3V | fixed |
Table 1720: Board bank voltages
Variants Currently in Production
| Board Variant | Xilinx Zynq SoC | DDR3L SDRAM | ARM Cores | PL Cells | LUTs | Flip-Flops | Block RAM | DSP Slices |
|---|---|---|---|---|---|---|---|---|
| TE0723-02 | XC7Z010-1CLG225C | 128 MBytes | Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 |
| TE0723-03M | XC7Z010-1CLG225C | 512 MBytes | Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 |
| TE0723-03-07S-1C | XC7Z007S-1CLG225C | 512 MBytes | Single-core | 23K | 14,4K | 28,8K | 1.8 MBytes | 66 |
Table 1821: Board variants
Technical Specifications
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Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
VIN supply voltage | -0.5 | 3.6 | V | Xilinx datasheet DS187. |
Storage temperature | -40 | +85 | °C |
Table 1922: Board absolute maximum ratings.
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| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| Supply voltage | 1.14 | 3.465 | V | Xilinx datasheet DS187. |
Table 2023: Board recommended operating conditions.
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| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| 2016-07-15 | 03 | Refer to Changes list in Schematic for further details in changes to REV02 | - | TE0723-03 |
2015-11-06 | 02 | Second Production Release | - | TE0723-02 |
| - | 01 | First Production Release | - | - |
Table 2124: Board hardware revision history
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Date | Revision | Contributors | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Ali Naseri, |
|
Table 2225: Document change history.
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