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The 7 boot mode strapping pins on the TE0723 module are set to boot the system from quad SPI Flash only. For additional information refer to the TE0723 schematic and Xilinx UG585 Zynq-7000 All Programmable SoC Technical Reference Manual section "Boot Mode Pin Settings".

You may also refer to this TE0723 reference design for some Boot Process tips.

Signals, Interfaces and Pins

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JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through FTDI USB/UART FIFO bridge connected to the J9 Micro USB connector.

Quad SPI Interface

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Quad SPI Flash (U14U5) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Note that table column says "Signal Name", it should match the name used on the schematic.

Zynq SoC's MIO	Signal Name	U14 U5 Pin
1	SPI-SPI0_CS	C21
2	SPI-SPI0_DQ0/M0MIO2	D35
3	SPI-SPI0_DQ1/M1MIO3	D22
4	SPI-SPI0_DQ2/M2MIO4	C43
5	SPI-SPI0_DQ3/M3MIO5	D47
6	SPI-SPI0_SCK/M4	B26

Table 3: Quad SPI interface signals and connections.

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TE0723 module has on-board 3.3V SD Card socket (J10) with card detect switch wired to the SoC PS MIO bank 500.

Zynq SoC's Pin	Connected To	Signal Name
MIO0	J10-9	Card detect switch
MIO10	J10-7	DAT0
MIO11	J10-3	CMD
MIO12	J10-5	CLK
MIO13	J10-8	DAT1
MIO14	J10-1	DAT3
MIO15	J10-2	CD/DAT3

Table 4: SD card socket signals.

USB Interface

Table x: USB interface.

ESP Wi-Fi Interface

Interface for the ESP8266 Wi-Fi module is provided through connector J5.

Table x: ESP8266 Wi-Fi module interface.

I2C Interface

I²C interface pins from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.

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