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Table 7: SD Card socket signals
USB Interface
High-speed USB2 interface is provided by USB3320 from Microchip (U18). The USB2 PHY is connected via ULPI interface to the Zynq SoC PS USB0, bank 501 and pins MIO28 ... MIO39.
| Zynq SoC U1 Pin | Signal Schematic Name | USB2 PHY U18 Pin |
|---|---|---|
| Bank 501, pin MIO28 | OTG-DATA4 | 7 |
| Bank 501, pin MIO29 | OTG-DIR | 31 |
| Bank 501, pin MIO30 | OTG-STP | 29 |
| Bank 501, pin MIO31 | OTG-NXT | 2 |
| Bank 501, pin MIO32 | OTG-DATA0 | 3 |
| Bank 501, pin MIO33 | OTG-DATA1 | 4 |
| Bank 501, pin MIO34 | OTG-DATA2 | 5 |
| Bank 501, pin MIO35 | OTG-DATA3 | 6 |
| Bank 501, pin MIO36 | OTG-CLK | 1 |
| Bank 501, pin MIO37 | OTG-DATA5 | 9 |
| Bank 501, pin MIO38 | OTG-DATA6 | 10 |
| Bank 501, pin MIO39 | OTG-DATA7 | 13 |
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Interface for the ESP8266 Wi-Fi module is provided through connector J5.
| Zynq SoC U1 Pin | Signal Schematic Name | Connected to |
|---|---|---|
| Bank 501, pin MIO48 | ESP_TXD | J5-2 |
| Bank 501, pin MIO49 | ESP_RXD | J5-7 |
| Bank 501, pin MIO52 | MOD_RST | J5-6 |
| Bank 501, pin MIO53 | ESP_GPIO0 | J5-3 |
| Bank 35, pin G15 | ESP_GPIO2 | J5-5 |
Table 6: ESP8266 Wi-Fi module interface
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I2C interface pins SCL and SDA from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C I²C slave devices.
| Zynq SoC U1 Pin | Signal Schematic Name | Connected to |
|---|---|---|
| R13 | SDA | J1-9 |
| P13 | SCL | J1-10 |
Table 7: Zynq SoC I2C interface
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On-board quad SPI Flash memory S25FL127S (U5) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the Zynq SoC's PS, allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
Dual High-speed USB to Multipurpose UART/FIFO
FT2232H... U3.
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FTDI FT2232H IC
The FTDI chip U3 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 14 I/O's of Channel B are routed to PL bank 34 of the Zynq SoC and are usable for example as UART interface.
The configuration of FTDI FT2232H chip is stored with Xllinx License on EEPROM U6. Please note the warning in section "USB2 to JTAG/UART Adapter" to not overwrite or delete the Xilinx License on the EEPROM U6
High-speed USB2 ULPI PHY
Hi-speed USB USB2 ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 3.3V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).
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There is a 2-Kbit (128 x 16-bit organization) Microwire compatible serial EEPROM 93AA56B (U6) connected to the FTDI FT2232H dual high-speed USB USB2 to multipurpose UART/FIFO (U3). This external EEPROM allows each of the FTDI FT2232H chip’s channels to be independently configured as a serial UART (RS232 mode), parallel FIFO (245) mode or fast serial (optical isolation). The external EEPROM can also be used to customize the USB VID, PID, serial number, product description strings and power descriptor value of the FT2232H for OEM applications. Other parameters controlled by the EEPROM include remote wake up, soft pull down on power-off and I/O pin drive strength.
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