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Refer to https://wiki.trenz-electronic.de/display/DRAFT/TE0723+TRM for downloadable version of this manual and additional technical documentation of the product.

 

The Trenz Electronic TE0723 is a Arduino compatible FPGA module based on the Xilinx Zynq XC7Z010 SoC.

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  1. Xilinx Zynq XC7Z010 SoC, U1
  2. 4 Gbit DDR3L 256M x 16 SDRAM, U2
  3. 16 MByte QSPI quad SPI Flash memory, U5
  4. High-speed CMOS logic analog multiplexer/demultiplexer, U10

  5. 1 MHz low-power operational amplifier, U11
  6. Dual high-speed USB to multipurpose UART/FIFO, U3
  7. 0.5A dual-channel current-limited power switch, U21
  8. Low-power programmable oscillator @ 12.000000 MHz, U7
  9. 2-Kbit Microwire compatible serial EEPROM, U6
  10. 10-pin header, J1
  11. 8-pin header, J2
  12. 10-pin header, J3
  13. Analog input header, J4
  14. 2 x 4-pin header, J5
  15. PMod 2x6 interface header, J6
  16. USB host mode jumper, J7
  17. Micro USB 2.0 Type-B receptacle, J8
  18. Micro USB 2.0 Type-B receptacle, J9
  19. Micro SD card connector with detect signal, J10
  20. Analog input select jumper, J11
  21. 5V supply power input, J12
  22. Reset switch, S1
  23. Red LED, D2
  24. Green LED, D6
  25. Green LED, D7
  26. Ultra-low supply-current voltage monitor, U23
  27. 1A PowerSoC DC-DC converter (3.3 V), U20

  28. 1A PowerSoC DC-DC converter (1.8 V, U19
  29. 1A PowerSoC DC-DC converter (1.35 V), U16
  30. Hi-speed USB 2.0 ULPI transceiver, U18
  31. Low-power programmable oscillator @ 52.000000 MHz, U14
  32. 1A PowerSoC DC-DC converter (1.0 V), U17
  33. JTAG interface testpoints, TP1-TP4

Initial Delivery State

Storage device name

IC

Content

Notes

Quad SPI Flash

U5

Empty

 
Microwire serial EEPROMU6Empty 

Table 1: Initial delivery state of programmable devices on the module.

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JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through FTDI USB/UART FIFO bridge connected to the J9 Micro USB connector.

Quad SPI Interface

Following line is just an example, change it to your needs.

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Note that table column says "Signal Name", it should match the name used on the schematic.

MIOSignal NameU14 Pin
1SPI-CSC2
2SPI-DQ0/M0D3
3SPI-DQ1/M1D2
4SPI-DQ2/M2C4
5SPI-DQ3/M3D4
6SPI-SCK/M4B2

Table x: Quad SPI interface signals and connections.

SD Card Interface

Describe SD Card interface  shortly here if the module has one...

FPGA / SoC PinConnected ToSignal NameNotes
MIO0J10-9Card detect switch 
MIO10J10-7DAT0 
MIO11J10-3CMD 
MIO12J10-5CLK 
MIO13J10-8DAT1 
MIO14J10-1DAT3 
MIO15J10-2CD/DAT3 

Default PS MIO Mapping

MIOFunctionConnected ToNotesMIOFunctionConnected ToNotes
0SDCARDJ10-9Card detect switch.28USB-OTGU18-7OTG-DATA4
1QSPIU5-1SP0-CS29USB-OTGU18-31OTG-DIR
2QSPIU5-5SPI0-DQ030USB-OTGU18-29OTG-STP
3QSPIU5-2SPI0-DQ131USB-OTGU18-2OTG-NXT
4QSPIU5-3SPI0-DQ232USB-OTGU18-3OTG-DATA0
5QSPIU5-7SPI0-DQ333USB-OTGU18-4OTG-DATA1
6QSPIU5-6SPI0-SCK34USB-OTGU18-5OTG-DATA2
7GPIOU18-27USB PHY reset35USB-OTGU18-6OTG-DATA3
9LEDD2Red LED36USB-OTGU18-1OTG-CLK
10SDCARDJ10-7DAT037USB-OTGU18-9OTG-DATA5
11SDCARDJ10-3CMD38USB-OTGU18-10OTG-DATA6
12SDCARDJ10-5CLK39USB-OTGU18-13OTG-DATA7
13SDCARDJ10-8DAT148ESPJ5-2ESP_TXD
14SDCARDJ10-1DAT249ESPJ5-7ESP_RXD
15SDCARDJ10-2CD/DAT352ESPJ5-6MOD_RST
    53ESPJ5-3ESP_GPIO0

USB Interface


ESP Interface


I2C Interface

I2C interface pins from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.

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Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 3.3V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).

Microwire Serial EEPROM

U36AA56BT-I/OT...

High-Speed Analog Multiplexer

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