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Table of Contents |
Overview
Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips.
Within the complete module only Automotive components are installed.
All this in a compact 6 x 6 cm form factor, at the most competitive price.
Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.
Key Features
Block Diagram
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Main Components
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- Xilinx XA7Z020-1CLG484Q (Automotive)
- Programmable Oscillator
- 2 x ARM Cortex-A9 MPCore
- 2 x 100 MBit Ethernet transceiver DP83848MPHPEP (PHY)
- 512 MByte DDR3 SDRAM, 16-bit-wide
- 16 MByte QSPI Flash memory (with XiP support)
- CAN transceiver (PHY)
- 12 V power supply with watchdog
- On-board high-efficiency DC-DC converters
- Three user LEDs
e
Initial Delivery State
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Storage device name | Content | Notes |
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.. | .. | .. | OTP Flash area | Empty | Not programmed. |
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Control Signals
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- Overview of Boot Mode, Reset, Enables,
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Signals, Interfaces and Pins
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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13 | JM1 | 48 | VCCO_13 |
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500 | JM1 | 4 | 3.3V |
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33 | JM3 | 34 | 3.3V |
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35 | JM3 | 20 | 3.3V |
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35 | JM2 | 22 | 3.3V |
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501 | JM2 | 38 | VMIO1 | MIO1 VREF is connected to resistor divider to support HSTL18 |
JTAG Interface
JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
JTAG Signal | B2B Pin |
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TMS | JM2-12 |
TDI | JM2-10 |
TDO | JM2-8 |
TCK | JM2-6 |
PS7 UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.
Subsections...
On-board Peripherals
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- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Chip/Interface | IC | PS7 Peripheral |
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SPI Flash | S25FL127SABMFV10 | QSPI0 | 16 MByte Flash |
I2C EEPROM | 24xx64 | I2C0 | 8 KByte EEPROM |
RTC I2C | RV-3029 | I2C0 |
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RTC Interrupt | RV-3029 | GPIO - MIO0 |
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User LED |
| GPIO - MIO7 |
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16 MByte Quad SPI Flash Memory
On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided here. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
RTC I2C
LED
Designator | Color | Connected to | Active Level | IO Standard |
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D9 | Green | DONE | Low | not applicable |
D8 | RED | MIO7 | High | LVCMOS33 |
D4 | Green | PL pin V18 | High | LVCMOS33 |
512 Mbyte DDR3L SDRAM
The TE0728 SoM has two 512 GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number: S25FL127 Spansion
- Supply voltage: 1.35V
- Speed: 1600 Mbps
- NOR Flash
- Temperature: 0C~95C
Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.
Ethernet
There are two 100 MBit Extreme Temperature Ethernet PHY's DP83848-EP provided by Texas Instrument on the board. Datasheet is provided here, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. All LED outputs have on-board pull-ups. Outputs to Magnetics have also required termination resistors on board.
Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.
| ETH1 | ETH2 | Pullup | Notes |
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CTREF | J3-57 | J3-25 |
| Magnetics center tap voltage |
TD+ | J3-58 | J3-28 | on-board |
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TD- | J3-56 | J3-26 | on-board |
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RD+ | J3-52 | J3-22 | on-board |
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RD- | J3-50 | J3-20 | on-board |
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LED1 | J3-55 | J3-23 | on-board |
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LED2 | J3-53 | J3-21 | on-board |
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LED3 | J3-51 | J3-19 | on-board |
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POWERDOWN/INT | L21 | R20 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used. |
RESET_N | M15 | R16 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset). |
It is recommended to add IOB TRUE constraint for the MII Interface pins.
When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.
Power and Power-On Sequence
Power Consumption
Power Distribution Dependencies
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Power-On Sequence
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Voltage Monitor Circuit
Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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VIN | 1,3 | - | - | Input |
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3.3 | 19 | 2, 4 | - | Output |
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1.8 | 39 | 5 | - | Output |
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Bank Voltages
Board to Board Connectors
Absolute Maximum Ratings
Technical Specifications
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Recommended Operating Conditions
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Physical Dimensions
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Variants Currently In Production
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Revision History
Hardware Revision History
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Date | Revision | Note | PCN | Documentation Link |
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- | 01 | Prototypes | - | - |
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title | Hardware Revision Number |
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Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
Document Change History
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Disclaimer
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| IN:Legal Notices |
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| IN:Legal Notices |
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