Page History

...

Scroll Title

anchor	Table_OV_IDS
title	Initial delivery state of programmable devices on the module.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
Quad SPI Flash	U13	Empty
DDR3 SDRAM	U1	Empty
24LC64	U11

Table 1: Initial state of programmable devices on delivery of the module.

Control Signals

Page properties

hidden	true
id	Comments

Overview of Boot Mode, Reset, Enables,

Boot Process

MODE Signal State	Boot Mode
High or open	QSPI

Table 2: Boot Process

Signals, Interfaces and Pins

...

FPGA Bank	B2B Connector	I/O Signal Count	Voltage Level	Notes
13	JM1	48	VCCO_13
500	JM1	4	3.3V
33	JM3	34	3.3V
35	JM3	20	3.3V
35	JM2	22	3.3V
501	JM2	38	VMIO1	MIO1 VREF is connected to resistor divider to support HSTL18

Table 3: Boot Process

JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

JTAG Signal	B2B Pin
TMS	JM2-12
TDI	JM2-10
TDO	JM2-8
TCK	JM2-6

Table 4: JTAG pins connection

PS7 UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

...

Chip/Interface	IC	PS7 Peripheral
SPI Flash	S25FL127SABMFV10	QSPI0	16 MByte Flash
I2C EEPROM	24LC64	I2C0	8 KByte EEPROM
RTC I2C	RV-3029	I2C0
RTC Interrupt	RV-3029	GPIO - MIO0
User LED	LED Green	GPIO - MIO7

Table 5: On board Peripherals

16 MByte Quad SPI Flash Memory

...

MIO Pin	Schematic	U13 Pin
MIO1	SPI_CS	A1
MIO2	SPI_DQ0/M0	A2
MIO3	SPI_DQ1/M1	F6
MIO4	SPI_DQ2/M2	E4
MIO5	SPI_DQ3/M3	A3
MIO6	SPI_SCK/M4	A4

Table 6: Quad SPI interface MIOs and pins

Supply Voltage: 2.7V to 3.6V

...

MIO Pin	Schematic	U7 Pin	Notes
MIO15	SDA	5	On-board RTC, and EEPROM
MIO14	SCL	4	On-board RTC, and EEPROM

Table 7: I²C interface MIOs and pins

I^₂C EEPROM

The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

...

MIO Pin	Schematic	U11 Pin	Notes
MIO15	SDA	3	On-board RTC, and EEPROM
MIO14	SCL	1	On-board RTC, and EEPROM

Table 8: I²C EEPROM interface MIOs and pins

LEDs

Schematic	Color	Connected to	Active Level	IO Standard
D9	Green	DONE	Low	not applicable
D8	RED	MIO7	High	not applicable
D4	Green	PL pin V18	High	LVCMOS33

Table 9: On-board LEDs.

512 Mbyte DDR3L SDRAM

The TE0728 SoM has two 512 GByte volatile DDR3 SDRAM IC for storing user application code and data.

...

Schematic	ETH1	ETH2	Pullup	Notes
CTREF	J3-57	J3-25		Magnetics center tap voltage
TD+	J3-58	J3-28	on-board
TD-	J3-56	J3-26	on-board
RD+	J3-52	J3-22	on-board
RD-	J3-50	J3-20	on-board
LED1	J3-55	J3-23	on-board
LED2	J3-53	J3-21	on-board
LED3	J3-51	J3-19	on-board
POWERDOWN/INT	L21	R20	on-chip	It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used.
RESET_N	M15	R16	on-chip	It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset).

Table 10: Ethernet PHY to Zynq SoC connections.

It is recommended to add IOB TRUE constraint for the MII Interface pins.

...

MIO Pin	Schematic	U16 Pin	Notes
MIO8	D	1
MIO9	R	4

Table 11: CAN Tranciever interface MIOs

Schematic	B2B	Pull up/down	Notes
CANH	J1-2	on-board
CANL	J1-4	on-board

Table 12: CAN Tranciever pins

Low Quiescent Current Programmable Delay Supervisory Circuit

...

IC	Description	Frequency	Used as
U14	MEMS Oscillator	50 MHz	PS PLL clock
U5	MEMS Oscillator	25 MHz	Ethernet PHY Clock
U7	RTC (internal oscillator)	32.768 KHz	Used by RTC, CLKOUT of RTC not connected

Table 13: Oscillators.

Power and Power-On Sequence

...

Power Input Pin	Typical Current
VIN	TBD*

Table 14: Power Consumption.

* TBD - To Be Determined

Power Distribution Dependencies

...

Power Rail Name	B2B Connector JM1 Pin	B2B Connector JM2 Pin	B2B Connector JM3 Pin	Direction
VIN	1,3	-	-	Input
VMIO	-	2	-	I/O
3.3V	19	4	25,57	Output
1.8V	-	5	-	Output

Table 14: Module power rails.

Bank Voltages

Bank	Schematic Name	Voltage	Notes
500	VCCO_MIO0_500	3.3V
501	VCCO_MIO1_500	3.3V
502	VCCO_DDR_502	1.5V
13 HR	VCCO_13	3.3V	Supplied by the carrier board. JM1
33 HR	VCCO_33	3.3V	Supplied by carrier board. JM3
34 HR	VCCO_34	3.3V
35 HR	VCCO_35	3.3V	Supplied by the carrier board. JM2,JM3

Table 15: Zynq SoC bank voltages.

Board to Board Connectors

...

Symbols	Description	Min	Max	Unit
VCCPINT	PS internal logic supply voltage	-0.5	1.1	V
VCCPAUX	PS auxiliary supply voltage	-0.5	2.0	V
VCCPLL	PS PLL supply	-0.5	2.0	V
VCCO_DDR	PS DDR I/O supply voltage	-0.5	2.0	V
VPREF	PS input reference voltage	-0.5	2.0	V
VCCO_MIO0	PS MIO I/O supply voltage for HR I/O banks	-0.5	3.6	V
VCCO_MIO1	PS MIO I/O supply voltage for HR I/O banks	1.71	3.45	V

Table 16: PS absolute maximum ratings.

Programmable Logic(PL)

Symbols	Description	Min	Max	Unit
VCCINT	PL internal logic supply voltage	-0.5	1.1	V
VCCPAUX	PL auxiliary supply voltage	-0.5	2.0	V
VCCPLL	PL PLL supply	-0.5	1.1	V
VPREF	PL input reference voltage	-0.5	2.0	V
VCCO	PL supply voltage for HR I/O banks	-0.5	3.6	V
VIN	I/O input voltage for HR I/O banks	1.71	3.45	V

Table 16: PL absolute maximum ratings.

Technical Specifications

Scroll Title

anchor	Table_TS_AMR
title	Module absolute maximum ratings.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Absolute Maximum Ratings

Parameter	Min	Max	Units	Reference Document
VIN supply voltage	3.5	60	V	TPS54260-Q1 datasheets.
Supply voltage for PS MIO banks	1.71	3.465	V	See Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks	-0.2	VCCO_MIO + 0.20	V	See Xilinx DS187 datasheet.
Supply voltage for PS DDR	1.14	1.89	V	See Xilinx DS187 datasheet.
I/O input voltage for PS DDR	-0.20	VCCO_DDR + 0.20	V	See Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks	1.14	3.465	V	See Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks	-0.20	VCCIO + 0.20	V	See Xilinx DS187 datasheet.
Storage Temperature	-65	150	°C	See Xilinx DS187 datasheet.
CAN Transceiver Temperature	-40	125	°C	See Texas Instrument sn65hvd230q-q1 datasheet.
SPI Flash Memory	-40	85	°C	See Cypress S25FL127S datasheet.
DDR3 SDRAM Temperature	-40	95	°C	See Nanya NT5CC256M16CP-DIA datasheet.

...

Table 17: Absolute Maximum Ratings..

Scroll Title

anchor	Table_TS_AMR
title	Recommended Operating Conditions.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Recommended Operating Conditions

Commercial grade: 0°C to +70°C.

...

Parameter	Min	Max	Units	Reference Document
VIN supply voltage	3.5	60	V	TPS54260-Q1 datasheets.
Supply voltage for PS MIO banks	1.71	3.465	V	See Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks	-0.2	VCCO_MIO + 0.20	V	See Xilinx DS187 datasheet.
Supply voltage for PS DDR	1.14	1.89	V	See Xilinx DS187 datasheet.
I/O input voltage for PS DDR	-0.20	VCCO_DDR + 0.20	V	See Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks	1.14	3.465	V	See Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks	-0.20	VCCIO + 0.20	V	See Xilinx DS187 datasheet.
Storage Temperature	-65	150	°C	See Xilinx DS187 datasheet.

Table 18: Recommended operating conditions.

Physical Dimensions

Scroll Title

anchor	Figure_TS_PD
title	Physical dimensions drawing

...

Schematic	Color	Connected to	Active Level	IO Standard
D9	Green	DONE	Low	not applicable
D8	RED	MIO7	High	not applicable
D4	Green	PL pin V18	High	LVCMOS33

512 Mbyte DDR3L SDRAM

The TE0728 SoM has two 512 GByte volatile DDR3 SDRAM IC for storing user application code and data.

...

Trenz Electronic Documentation

Versions Compared

Old Version 107

New Version 108

Key

Control Signals

Boot Process

Signals, Interfaces and Pins

JTAG Interface

PS7 UART

16 MByte Quad SPI Flash Memory

I^₂C EEPROM

Low Quiescent Current Programmable Delay Supervisory Circuit

Power and Power-On Sequence

Power Distribution Dependencies

Bank Voltages

Board to Board Connectors

Programmable Logic(PL)

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

512 Mbyte DDR3L SDRAM

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 107

New Version 108

Key

Control Signals

Boot Process

Signals, Interfaces and Pins

JTAG Interface

PS7 UART

16 MByte Quad SPI Flash Memory

I2C EEPROM

Low Quiescent Current Programmable Delay Supervisory Circuit

Power and Power-On Sequence

Power Distribution Dependencies

Bank Voltages

Board to Board Connectors

Programmable Logic(PL)

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

512 Mbyte DDR3L SDRAM

I^₂C EEPROM