Page History

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1. 512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
3. 100 MBit Ethernet transceiver  DP83848, U3
4. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
5. Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
6. 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
7. Real Time Clock, Micro Crystal @32.768 MHz, 3.3V, RV-3029-C3, U7
8. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
9. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
10. 100 MBit Ethernet transceiver  DP83848MPHPEP, U10
11. 64 Kbit I2C EEPROM, 24LC64, U11
12. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
13. 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
14. Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
15. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
16. CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16
    
    

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On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided here. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

RTC I^₂C

The RV-3029-C3 is an ultra miniature Real-Time-Clock Module with embedded Crystal. This RTC has an I²C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy of ± 6ppm from -40°C to +85°C and ± 8ppm from -40°C to +125°C.

EEPROM

EEPROM

The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

LEDs

LEDs

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There are two 100 MBit Extreme Temperature Ethernet PHY's DP83848Ethernet  DP83848-EP are provided by Texas Instrument on the board. Datasheet is provided TI website, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

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Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.

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