Page History
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| PHY Pin | Connected to | Notes |
|---|---|---|
| MDC/MDIO | PS bank MIO76, MIO77 | - |
| PHY LED0..1 | SC CPLD U17, pin 67,86 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
| PHY_LED2 / INTn: | SC CPLD U17, pin 85 | Active low interrupt line |
| PHY_CLK125M | SC CPLD U17, pin 70 | 125 MHz Ethernet PHY clock out |
| CONFIG | SC CPLD U17, pin 65Permanent logic high | Configuration of PHY address LSB and VDDO level |
| RESETn | SC CPLD U17, pin 62 | Active low reset line |
| RGMII | PS bank MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
| SGMII | - | Serial Gigabit Media Independent Interface |
| MDI | RJ45 GbE MagJack J7 | Media Dependent Interface |
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Overview
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