Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Scroll Title
anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO PinSchematicU13 PinNotes
MIO1SPI_CSU13-A1
MIO2SPI_DQ0/M0U13-A2
MIO3SPI_DQ1/M1U13-F6
MIO4SPI_DQ2/M2U13-E4
MIO5SPI_DQ3/M3U13-A3
MIO6SPI_SCK/M4U13-A4


RTC 

The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

...

Scroll Title
anchorTable_OBP_RTC
titleI2C interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO PinSchematicU7 PinNotes
MIO15SDAU7-5On-board RTC, and EEPROM
MIO14SCLU7-4On-board RTC, and EEPROM


...

Scroll Title
anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO PinSchematicU11 PinNotes
MIO15SDAU11-3On-board RTC, and EEPROM
MIO14SCLU11-1On-board RTC, and EEPROM


...

When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.

...

Scroll Title
anchorTable_OBP_CAN
titleCAN Tranciever interface MIOs

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO PinSchematicU16 PinNotes
MIO8DU16-1
MIO9RU16-4


Low Quiescent Current Programmable Delay Supervisory Circuit

...