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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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| 13 | HR | J1 | 48(24) | VCCO_13 | variable from carrier | | 500 | HR | J1 | 4 | 3.3V |
| | 501 | HR | J2 | 37 | VMIO1 | variable from carrier | | 33 | HR | J3 | 34 | 3.3V |
| | 35 | HR | J3 | 20 | 3.3V |
| | 35 | HR | J2 | 22 | 3.3V |
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Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.
| Scroll Title |
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| anchor | Table_SIP_B2B_Eth |
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| title | Ethernet PHY B2B connectors. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | ETH1 | ETH2 | Pullup | Notes |
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| CTREF | J3-57 | J3-25 |
| Magnetics center tap voltage | | TD+ | J3-58 | J3-28 | on-board |
| | TD- | J3-56 | J3-26 | on-board |
| | RD+ | J3-52 | J3-22 | on-board |
| | RD- | J3-50 | J3-20 | on-board |
| | LED1 | J3-55 | J3-23 | on-board |
| | LED2 | J3-53 | J3-21 | on-board |
| | LED3 | J3-51 | J3-19 | on-board |
| | POWERDOWN/INT | L21 | R20 | on-chip |
| | RESET_N | M15 | R16 | on-chip | Active low PHY Reset |
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| Scroll Title |
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| anchor | Table_SIP_B2B_CAN |
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| title | CAN B2B connectors.General PL I/O to B2B connectors information |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
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|
FPGA Bank Connector| I/O Signal Count | 1348(24) | VCCO_13 | variable from carrier | 500 | J1 | 4 | 3.3V | | 501 | J2 | 37 | VMIO1 | variable from carrier | 33 | J3 | 34 | 3.3V | 35 | J3 | 20 | 3.3V | | -2 |
| Magnetics center tap voltage | | CANL | J1-4 | on-board |
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JTAG Interface
JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
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| Scroll Title |
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| anchor | Table_OBP_MIOs |
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| title | MIOs pins |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | Notes |
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| MIO0 | MIO0 | RTC interrupt | | MIO1 | SPI_CS | SPI Flash | | MIO2-5 | SPI_DQ0-3/M0-3 | SPI Flash | | MIO6 | SPI_SCK/M4 | SPI Flash clock | | MIO7 | LED RED | LED | | MIO8 | D | CAN Transceiver | | MIO9 | R | CAN Transceiver | | MIO10 | IO_0 | J1-7 | | MIO11 | IO_1 | J1-9 | | MIO12 | IO_2 | J1-11 | | MIO13 | IO_3 | J1-13 | | MIO14 | SCL | EEPROMI2C | | MIO15 | SDA | EEPROMI2C | | MIO16-MIO53 | PS_MIOxx |
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On-board Peripherals
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| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | Zynq SoC bank voltages. |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
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| Schematic Name | | HR I/O Bank | Notes |
|---|
| 500 | VCCO_MIO0_500 | 3.3V | Supported |
| | 501 | VCCO_MIO1_500 | Variable |
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| | 502 | VCCO_DDR_502 | 1.5V | Supported |
| | 13 HR | VCCO_13 | Variable | Supported | Supplied by the carrier board. J1 | | 33 HR | 3.3V | 3.3V | Supported | Supplied by carrier board. J3 | | 34 HR | 3.3V | 3.3V | Supported |
| | 35 HR | 3.3V | 3.3V | Supported | Supplied by the carrier board. J2, J3 |
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