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Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1 and JB2:
| B2B Connector | Interfaces | Count of IO's | Interfaces | Notes |
|---|---|---|---|---|
| JB1 | User IO | 24 single ended | - | |
| User IO- | 48 single ended or 24 differential | User IO | - | |
| JB2 | User IO | 54 single ended | - | |
| User IO | - | 10 single ended or 5 differential | User IO-- | |
| I²C | 2 | I²C | - | |
| 7 | SD IO | 7 | - | |
| UART | 2 | UART | - | 6|
| USB2.0 | 6 | - | ||
| 14 | 2x 10/100-BaseT Ethernet | 14 | - | 14|
| GbE MDI and SGMII | 14 | - | ||
| JTAG | 4 | JTAG | - |
Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
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Following table gives a summary of the pin-assignment, available interfaces and functional IO's of the VG96 connectors J8 and J9:
:
| VG96 Connector | Control Signals and Interfaces | |||
|---|---|---|---|---|
| VG96 Connector | Count of PL IO's | Count of LVDS-pairs | SoM Control Signals and Interfaces | Notes |
| J8 | 72 | 24 | - | - |
| J9 | 64 | 5 | 'NRST_IN', pin J9-A29 | Drive to ground (Push Button S1, JB3-11 (G) on XMOD header) to reset the SoM. 2) |
| 'NRST_OUT', pin J9-B30 | Incoming reset signal from SoM's watchdog (implemented on SoM's SC CPLD). 2) | |||
| 'BOARD_STAT', pin J9-B32 | Frequently flipping signal indicating running SoM. Routed also to XMOD Header, pin JB3-9 (E). | |||
| 'BOOT_MODE1', pin J9-C31 | Bootmode pin 1, use in conjunction with Bootmode pin 2. | |||
| 'BOOT_MODE2', pin J9-C32 | Bootmode pin 2, use in conjunction with Bootmode pin 1. | |||
| I²C, pins J9-A30, J9-A31 | I²C1 interface of module. | |||
| GbE SGMII, pins J9-A16, J9-A17, J9-A19 J9-A20 | SGMII interface of on-module GbE PHY. | |||
| VG96 Connector | Count of IO'sControl Signals and Interfaces | Notes | ||
| J8 | User IO | 24 single ended | - | |
| User IO | - | 48 single ended or 24 differential | User IO | - |
| J9 | User IO | 54 single ended | - | |
| User IO | - | 10 single ended or 5 differential | User IO | - |
| 2 | 'NRST_IN', 'NRST_OUT', pins J9-A29, J9-B30 | 2 | SoM reset signals 1) | |
| 'BOARD_STAT', pin pins J9-B32 | 1 | - | 2||
| 'BOOT_MODE1', 'BOOT_MODE2' pin , pins J9-C31, J9-C32 | - | 22 | Binary bootmode code of SoM | |
| I²C, pins J9-A30, J9-A31 | - | 42 | I²C1 interface of module | |
| GbE SGMII | 4 | SGMII interface of on-module GbE PHY |
Table 3: General overview of PL I/O signals, SoM's interfaces and control signals connected to the VG96 connectors.
HW-modification Concerning Reset-Signals
21) The pins with the schematic net names 'NRST_IN' (JB2-89) and 'NRST_OUT' (JB2-91) are swapped as part of a HW-modification to rework the Reset-signals of the Carrier-Board in conjunction with the TE0729 SoM.
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| JB3 pin | Signal Schematic Net Name | B2B | Note |
|---|---|---|---|
| C (pin 4) | TCK | JB2-119 | - |
| D (pin 8) | TDO | JB2-117 | - |
| F (pin 10) | TDI | JB2-115 | - |
| H (pin 12) | TMS | JB2-113 | - |
| A (pin 3) | USART0_TX | JB2-96 | - |
| B (pin 7) | USART0_RX | JB2-94 | - |
| E (pin 9) | BOARD_STAT | JB2-112 | also connected to VG96 connector pin J9-B32 |
| G (pin 11) | NRST_IN 32) | JB2-89 | also connected to VG96 connector pin J9-A29 |
Table 12: XMOD header signals and connections. 32) Swapped at HW-Modification with signal 'NRST_OUT' in board-revision 2
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