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The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.
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Voltage Monitor Circuit
Power Rails
| Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
|---|---|---|---|---|---|
| VIN | 1,3 | - | - | Input | |
| VMIO | - | 2 | - | I/O | |
| 3.3V | 19 | 4 | 25,57 | Output | |
1.8V | - | 5 | - | Output |
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Bank | Schematic Name | Voltage | Notes | ||
|---|---|---|---|---|---|
| 500 | 3.3V, VCCO_MIO0_500 | 3.3V | |||
| 501 | VMIO, VCCO_MIO1_500 | 3.3V | |||
| 502 | 1.5V, VCCO_DDR_502 | 1.5V | |||
| 13 HR | VCCO13 | 1.2V toVCCO_13 | 3.3V | Supplied by the carrier board. JM1-39 | |
| 33 HR | VCCO33 | 1.2V toVCCO_33 | 3.3V | Supplied by carrier board. JM3-25, JM3-57, JM2-4 | |
| 34 HR | VCCO33 | 1.25V toVCCO_34 | 3.3V | Supplied by the carrier board.||
| 35 HR | VCCO35 | 1.2V toVCCO_35 | 3.3V | Supplied by the carrier board. JM2,JM3 |
Board to Board Connectors
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| Parameter | Min | Max | Units | Reference Document
| Symbols | Description | Min | Max | Unit |
|---|---|---|---|---|
| VCCPINT | PS internal logic supply voltage | 0.95 | 1.05 | V |
| VCCPAUX | PS auxiliary supply voltage | 1.71 | 1.89 | V |
| VCCPLL | PS PLL supply | 1.71 | 1.89 | V |
| VCCO_DDR | PS DDR I/O supply voltage | 1.14 | 1.89 | V |
| VCCO_MIO0 | PS MIO I/O supply voltage for MIO banks | 1.71 | 3.45 | V |
| VCCO_MIO1 | PS MIO I/O supply voltage for MIO banks | 1.71 | 3.45 | V |
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. |
| Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
Physical Dimensions
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Overview
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