Page History

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Basic Notes
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Overview

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General Design description
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Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.

Key Features

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Revision History

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- Export PDF to download, if vivado revision is changed!
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• additional notes for FSBL generated with Win SDK
• changed *.bif

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• new assembly variant

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• Update Board Part for TEBF0808
  • no changes for test board design and minimal board parts

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• rework Board Part Files

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TE0808-test_board-vivado_2017.2-build_07_20171220192501.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_07_20171220192448.zip

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• Update Board Part Files

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• Update Board Part CSV File
• Regenerate design

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Overview

Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

Revision History

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• Update Board Part CSV File with new Flash assembly variants

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• initial release

Release Notes and Know Issues

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Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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Xilinx has stopped ES1 support with 2018.2, please use 2017.4 reference design

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Note: Design contains also Board Part Files for TE0808+TEBF0808 configuration, this boart part files are not used for this reference design.

Design supports following carriers:

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

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Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design.

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0808 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Vivado/SDK/SDSoC
• Vivado Projects
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Added
2. Press 0 and enter to start "Module Selection Guide"
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
   
   1. S(optional for manual changes)elect correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
      Important: Use Board Part Files, which did not ends with *_tebf0808
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP

SD

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with SDK Debugger into device, see:

• SDK Projects
• SDK Projects#DebugSoftwareApplication

Usage

QSPI Boot:

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Select QSPI Card as Boot Mode
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from QSPI into OCM, 2. FSBL loads Application into DDR

Debugging:

• SDK Projects
• SDK Projects#DebugSoftwareApplication

System Design - Vivado

Block Design

Scroll Title
anchor Figure_BD title Block Design
Image Added

PS Interfaces

Activated interfaces:

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - SDK/HSI

For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 2018.3 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
• Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
• General Changes: 
  
  • Display FSBL Banner and Device Name

zynqmp_fsbl_flash

TE modified 2018.3 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

hello_te0808

Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Additional Sources

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Prebuilt

<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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File

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File-Extension

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Description

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Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
  -->

Reference Design is available on:

• TE0808 "Test Board" Reference Design

Design Flow

<!--
Basic Design Steps
Add/ Remove project specific 
  -->

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Vivado/SDK/SDSoC
• Vivado Projects
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Removed
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which did not ends with *_tebf0808
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

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Description of Block Design, Constrains...
BD Pictures from Export...
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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

<!--
Example:
Connect JTAG and power on PCB
(if not done) Select 
correct device and Xilinx install path on "design_basic_settings.cmd" 
and create Vivado project with "vivado_create_project_guimode.cmd" or 
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

   -->

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP

SD

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with SDK Debugger into device, see:

• SDK Projects
• SDK Projects#DebugSoftwareApplication

Usage

QSPI Boot:

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Select QSPI Card as Boot Mode
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from QSPI into OCM, 2. FSBL loads application into DDR

Debugging:

• SDK Projects
• SDK Projects#DebugSoftwareApplication

System Design - Vivado

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Description of Block Design, Constrains...
BD Pictures from Export...
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Block Design

Image Removed

PS Interfaces

Activated interfaces:

...

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - SDK/HSI

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optional chapter
separate sections for different apps
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For SDK project creation, follow instructions from:

SDK Projects

Application

zynqmp_fsbl

Xilinx default FSBL

zynqmp_fsbl_flash

TE modified 2018.2 FSBL

Changes:

• Set FSBL Boot Mode to JTAG
• Disable Memory initialisation

hello_te0808

Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

<!--
Add Description for other Software, for example SI CLK Builder ...
 -->

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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...

...

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Legal Notices

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