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title	TE0728 block diagram

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Figure 1: TE0728 Block Diagram

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Boot Process

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MODE Signal State	Boot Mode
High or open	QSPI

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FPGA bank number and number of I/O signals connected to the B2B connector:

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title	General PL I/O to B2B connectors information

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FPGA Bank	B2B Connector	I/O Signal Count	Voltage Level	Notes
13	JM1	48	VCCO_13
500	JM1	4	3.3V
33	JM3	34	3.3V
35	JM3	20	3.3V
35	JM2	22	3.3V
501	JM2	38	VMIO1	MIO1 VREF is connected to resistor divider to support HSTL18

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JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal	B2B Pin
TMS	JM2-12
TDI	JM2-10
TDO	JM2-8
TCK	JM2-6

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Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

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MIO Pin	Schematic	U13 Pin
MIO1	SPI_CS	A1
MIO2	SPI_DQ0/M0	A2
MIO3	SPI_DQ1/M1	F6
MIO4	SPI_DQ2/M2	E4
MIO5	SPI_DQ3/M3	A3
MIO6	SPI_SCK/M4	A4

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The RV-3029-C3 is an ultra miniature Real-Time-Clock Module with embedded Crystal. This RTC has an I²C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy of ± 6ppm from -40°C to +85°C and ± 8ppm from -40°C to +125°C.

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MIO Pin	Schematic	U7 Pin	Notes
MIO15	SDA	5	On-board RTC, and EEPROM
MIO14	SCL	4	On-board RTC, and EEPROM

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The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

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title	I2C EEPROM interface MIOs and pins

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MIO Pin	Schematic	U11 Pin	Notes
MIO15	SDA	3	On-board RTC, and EEPROM
MIO14	SCL	1	On-board RTC, and EEPROM

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LEDs

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Schematic	Color	Connected to	Active Level	IO Standard
D9	Green	DONE	Low	not applicable
D8	RED	MIO7	High	not applicable
D4	Green	PL pin V18	High	LVCMOS33

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Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.

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title	Ethernet PHY to Zynq SoC connections

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Schematic	ETH1	ETH2	Pullup	Notes
CTREF	J3-57	J3-25		Magnetics center tap voltage
TD+	J3-58	J3-28	on-board
TD-	J3-56	J3-26	on-board
RD+	J3-52	J3-22	on-board
RD-	J3-50	J3-20	on-board
LED1	J3-55	J3-23	on-board
LED2	J3-53	J3-21	on-board
LED3	J3-51	J3-19	on-board
POWERDOWN/INT	L21	R20	on-chip	It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used.
RESET_N	M15	R16	on-chip	It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset).

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The SN65HVD230Q, controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is avaiable in Texas Instrumens website. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Temperature must be in range of -40°C ~125°C .

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MIO Pin	Schematic	U16 Pin	Notes
MIO8	D	1
MIO9	R	4

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Clock Sources

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IC	Description	Frequency	Used as
U14	MEMS Oscillator	50 MHz	PS PLL clock
U5	MEMS Oscillator	25 MHz	Ethernet PHY Clock
U7	RTC (internal oscillator)	32.768 KHz	Used by RTC, CLKOUT of RTC not connected

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors
Include Page
PD:4 6 x 5 6 SoM LSHM B2B Connectors
PD:4 6 x 5 6 SoM LSHM B2B Connectors

6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

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Module size: 60 mm × 60 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 7 mm.
PCB thickness: 1.6 mm.

Variants Currently In Production

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Variants Currently In Production

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Set correct link to the shop page overview table of the product on English and German, if not available, set
Set correct link to the shop page overview table of the product on English and German, if not available, set
- https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/
- https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/

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title	Trenz Electronic Shop Overview

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Trenz shop TE0728 TE0728 overview page
English page	German page

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Trenz Electronic Documentation

Versions Compared

Old Version 121

New Version 122

Key

Boot Process

Clock Sources

Variants Currently In Production

Variants Currently In Production