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| Scroll Title |
|---|
| anchor | Figure_PWR_PS |
|---|
| title | Power On Sequence |
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|
| Scroll Ignore |
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| draw.io Diagram |
|---|
| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | false |
|---|
| revision | 67 |
|---|
| diagramName | PWR_PS |
|---|
| simpleViewer | false |
|---|
| width | 600 |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramWidth | 641 |
|---|
|
|
| Scroll Only |
|---|
| scroll-pdf | true |
|---|
| scroll-office | true |
|---|
| scroll-chm | true |
|---|
| scroll-docbook | true |
|---|
| scroll-eclipsehelp | true |
|---|
| scroll-epub | true |
|---|
| scroll-html | true |
|---|
| | draw.io Diagram |
|---|
| border | true |
|---|
| viewerToolbar | true |
|---|
| fitWindow | false |
|---|
| diagramName | PWR_PS |
|---|
| simpleViewer | false |
|---|
| width | 600 |
|---|
diagramWidth | 641 | |
|
Power Distribution Dependencies
| Scroll Title |
|---|
| anchor | Figure_PWR_PD |
|---|
| title | Power Dependencies |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | false |
|---|
| revision | 1 |
|---|
| diagramName | TE7028_PWR_PD |
|---|
| simpleViewer | false |
|---|
| width | 400 |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramWidth | 601 |
|---|
|
|
| Scroll Only |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| viewerToolbar | true |
|---|
| fitWindow | false |
|---|
| diagramName | TE7028_PWR_PD |
|---|
| simpleViewer | false |
|---|
| width | 400 |
|---|
diagramWidth | 601 |
|---|
|
|
The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.
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