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Clock Signal Schematic Name
FMC Connector PinsDirectionClock SourceNotes
B228_CLK0J5-D4 / J5-D5inFMC Connector J5Extern MGT clock
B229_CLK0J5-B20 / J5-B21inFMC Connector J5Extern MGT clock
FMCCLK2J5-K4 / J5-K5outCarrier Board PLL SI5338A U35, CLK2Clock signal to Mezzanine module
FMCCLK3J5-J2 / J5-J3outCarrier Board PLL SI5338A U35, CLK3Clock signal to Mezzanine module
B64_L14_P / B64_L14_NJ5-H4 / J5-H5inFMC Connector J5Extern LVDS Clock clock to PL bank
B48_L6_P / B48_L6_NJ5-G2 / J5-G3inFMC Connector J5Extern LVDS Clock clock to PL bank

Table 5: FMC connector pin-outs for reference clock output

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Signal Schematic NameFPGA DirectionDescriptionLogic
WAKEInputLink reactivationLow active
PERSTOutputPCI Express reset inputLow active
PRSNT1InputReference pin for PCIe Card card lane size-
PRSNT2InputPCI Express ×1 cardsconnect to PRSNT1
PRSNT3InputPCI Express ×4 cardsconnect to PRSNT1
PRSNT4InputPCI Express ×8 cardsconnect to PRSNT1
PRSNT5InputPCI Express ×16 cardsconnect to PRSNT1
PCIE_I²CBiDir2-wire PCIE System Management Bus-

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