Versions Compared

Old Version 15

changes.mady.by.user Ali Naseri

Saved on

compared with

New Version 16

changes.mady.by.user Ali Naseri

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Following table contains the assignment of the MIO pins to the configured interfaces:

MIOConfigured asAlternateNotes
0..12Dual QSPI-Dual Flash Memory on TE0808 SoM; Bootable
13..23SD0: eMMC-eMMC Memory U2; Bootable
24, 25 -CPLD (U39) MUXED -
26..29PJTAG0CPLD (U17 MUXEDBootable JTAG
30 -CPLD (U39) MUXED -
31PCIeCPLD (U39) MUXEDSame as ZCU102
32 -CPLD (U39) MUXED -
33PMUCPLD (U39) MUXEDSame as ZCU102
34..37DisplayPort AuxCPLD (U39) MUXED -
38, 39I2C0- -
40, 41CAN1CPLD (U39) MUXED -
42, 43UART0CPLD (U39) MUXED -
44I2C InterruptCPLD (U39) MUXED -
45..51SD1: SD-Bootable MikeoSD / MMC Card
52..63USB0- -
64..75GEM3-Ethernet RGMII
76, 77MDC / MDIO -Ethernet RGMII

Table 5:  MIO Assignment

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by the IC U4, Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub. The pin-strap configuration option of the USB3.0 Hub U4 is disabled, so the Hub will only be configurable over the configuration EEPROM U5. The I²C interface of the EEPROM is also accessible by the MPSoC through I²C switch U16.

...

  • SATA (PS GT bank 505, MGT2 Lane)
  • Display-Port (PS GT bank 505, MGT3 Lane, only TX-pair routed)
  • PCI Express (PS GT bank 505, MGT0 Lane)

FunctionMGT LaneRef ClockClock SourceComment
PCIePS 0100 MHzSi5345 (CLK0 of prog. PLL on mounted SoM) -
USB3PS 1100 MHzOptional Oscillator U6 -
SATAPS 2150 MHzOscillator U23 -
DP.0PS 327 MHz-Display Port

Table 6:  PS GT Lane Assignment

...

The TEBF0808 carrier board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) and Samtec "FireFly". Each of this connectors are capable of data transmission rates up  to 10 Gbit/s.

FunctionMGT LaneRef ClockClock SourceComment
FireFlyB128 MGT Lanes 0..3-- -
SFPB230 MGT Lane 2125/156.25 MHzSi5345 (CLK7 of prog. PLL on mounted SoM) -
SFPB230 MGT Lane 3125/156.25 MHzSi5345 (CLK7 of prog. PLL on mounted SoM) -

Table 6:  MGT Lane Assignment

...

Additionally the carrier board provides PMOD connectors with GPIO and I²C interface. Following table

PMODInterfaceConnected withNotes
P1GPIOHP Bank 65 of MPSoC (4 I/O's)
System Controller CPLD U17  (I/O's)		Voltage translation via IC U33 with direction control,
only singled-ended signaling possible
P2I²C8-channel I²C Switch U27Accessible on MPSoC's I²C interface
P3I²C8-channel I²C Switch U27Accessible on MPSoC's I²C interface

Table 7:  PMOD Pin Assignment

...

  • Reset Button
  • Power Button
  • Power LED
  • Hard Disc (HD) LED
  • Intel High Definition Audio (HDA) Jacks

 

 

Header
Pins
Pin NameFunctionConnected to
Function
Notes
J10

Pin 1, HD LED+
Pin 3, HD LED-
Pin 2, PWRLED+
Pin 4, PWRLED-
Pin 5, GND
Pin 7, RSTSW
Pin 6, PWRSW
Pin 8, GND
Pin 9, +5V DC

SC CPLD U39

HD LED Anode
HD LED Cathode
Power LED Anode
Power LED Cathode
Ground
Reset Switch
Power Switch
Ground
5V DC

Power

Supply

SC CPLD U39




also connected to switch button S1
also connected to switch button S2
J9

Pin 1, PORT1L
Pin 3, PORT1R
Pin 9, PORT2L
Pin 5, PORT2R
Pin 7, SENS_SEND

24-bit Audio Codec IC U3

Pin 2, GND

Microphone Jack Left
Microphone Jack Right
Audio Out Jack Left
Audio Out Jack Right
Jack Detect / Mic in
Ground		24-bit Audio Codec IC U3-
J23Pin 1, 3V3SB
Pin 4, S1
SC CPLD U39
3.3V DC Supply
PC compatible Beeper		SC CPLD U39-
J26

Pin 1, GND
Pin 2, 12V
Pin 3, F1SENSE
Pin 4, F1PWM

Ground
12V DC Supply
RPM
PWM		SC CPLD U394-wire PWM FAN connector
-J35
J35

Pin 1, GND
Pin 2, 12V
Pin 3, F2SENSE
Pin 4, F2PWM

Ground
12V DC Supply
RPM
PWM		SC CPLD U39

4-wire PWM FAN connector

optional load switch U48 to turn off/on FAN
with pin F2_EN

J19

Pin 1, GND
Pin 2, 5V

Ground
5V DC Supply
-
Load Switch Q3 (5V DCDC)2-wire FAN connector

Fan off/on switchable by signal 'FAN_FMC_EN'
on SC CPLD U39

Table 8: PC compatible Headers

 

Figure 7: TEBF0808 PC Compatible Headers

JTAG Interface

The TEBF0808 carrier board provides several JTAG interfaces to program both the System Controller CPLDs and the Zynq Ultrascale+ MPSoC.

Therefore, the board is equipped with two JTAG/UART headers, which have 'XMOD-FT2232H FTDI JTAG Adapter'-compatible pin-assignment