Page History

...

Scroll Title

anchor	Table_OV_IDS
title	Initial delivery state of programmable devices on the module.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
Quad SPI Flash	U13	Empty
DDR3 SDRAM	U1	Empty
24LC64	U11

...

Scroll Title

anchor	Table_BP
title	Boot Processprocess.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MODE Signal State	Boot Mode
High or open	QSPI

...

Scroll Title

anchor	Table_B2B
title	General PL I/O to B2B connectors information.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

FPGA Bank	B2B Connector	I/O Signal Count	Voltage Level	Notes
13	JM1	48	VCCO_13
500	JM1	4	3.3V
33	JM3	34	3.3V
35	JM3	20	3.3V
35	JM2	22	3.3V
501	JM2	38	VMIO1	MIO1 VREF is connected to resistor divider to support HSTL18

...

Scroll Title

anchor	Table_JTG
title	JTAG pins Connectionconnection

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

JTAG Signal	B2B Pin
TMS	JM2-12
TDI	JM2-10
TDO	JM2-8
TCK	JM2-6

...

Scroll Title

anchor	Table_LED
title	On-board LEDs.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Color	Connected to	Active Level	IO Standard
D9	Green	DONE	Low	not applicable
D8	RED	MIO7	High	not applicable
D4	Green	PL pin V18	High	LVCMOS33

...

Scroll Title

anchor	Table_ETH
title	Ethernet PHY to Zynq SoC connections.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	ETH1	ETH2	Pullup	Notes
CTREF	J3-57	J3-25		Magnetics center tap voltage
TD+	J3-58	J3-28	on-board
TD-	J3-56	J3-26	on-board
RD+	J3-52	J3-22	on-board
RD-	J3-50	J3-20	on-board
LED1	J3-55	J3-23	on-board
LED2	J3-53	J3-21	on-board
LED3	J3-51	J3-19	on-board
POWERDOWN/INT	L21	R20	on-chip	It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used.
RESET_N	M15	R16	on-chip	It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset).

...

title

Scroll Title

anchor	Table_CAN_MIO
title	CAN Tranciever interface MIOs

anchor

Table_CAN

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin	Schematic	U16 Pin	Notes
MIO8	D	1
MIO9	R	4

Scroll Title

CAN Tranciever pins.

Scroll Table Layout

orientation

portrait

sortDirection

ASC

repeatTableHeaders

default

style

widths

sortByColumn

1

sortEnabled

false

cellHighlighting

true

MIO Pin

Schematic

U16 Pin

Notes

MIO8

D

1

MIO9

R

4

Low Quiescent Current Programmable Delay Supervisory Circuit

...

Scroll Title

anchor	Table_PWR_PC
title	Power Consumption.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Input Pin	Typical Current
VIN	TBD*

...

Trenz Electronic Documentation

Versions Compared

Old Version 119

New Version 120

Key

Low Quiescent Current Programmable Delay Supervisory Circuit