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| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MODE Signal State | Boot Mode |
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High or open | QSPI |
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Signals, Interfaces and Pins
| Page properties |
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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| 13 | JM1 | 48 | VCCO_13 |
| | 500 | JM1 | 4 | 3.3V |
| | 33 | JM3 | 34 | 3.3V |
| | 35 | JM3 | 20 | 3.3V |
| | 35 | JM2 | 22 | 3.3V |
| | 501 | JM2 | 38 | VMIO1 | MIO1 VREF is connected to resistor divider to support HSTL18 |
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JTAG
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Interface
JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Chip/Interface | IC | PS7 Peripheral | Notes |
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| SPI Flash | S25FL127SABMFV10 | QSPI0 | 16 MByte Flash | | I2C EEPROM | 24LC64 | I2C0 | 64 KByte EEPROM | | RTC I2C | RV-3029 | I2C0 |
| | RTC Interrupt | RV-3029 | GPIO - MIO0 |
| | User LED | LED Green | GPIO - MIO7 |
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16 MByte Quad SPI Flash Memory
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On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
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Supply Voltage: 2.7V to 3.6VTable 6: Quad SPI interface MIOs and pins
Temperature Range:
- Industrial (-40°C to +85°C)
- Industrial Plus (-40°C to +105°C)
- Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
- Automotive AEC-Q100 Grade 2 (-40°C to +105°C)
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| Scroll Title |
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| anchor | Table_OBP_RTC |
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| title | I2C interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U7 Pin | Notes |
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| MIO15 | SDA | 5 | On-board RTC, and EEPROM | | MIO14 | SCL | 4 | On-board RTC, and EEPROM |
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I2C EEPROM
The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.
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| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U11 Pin | Notes |
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| MIO15 | SDA | 3 | On-board RTC, and EEPROM | | MIO14 | SCL | 1 | On-board RTC, and EEPROM |
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LEDs
| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Color | Connected to | Active Level | IO Standard |
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| D9 | Green | DONE | Low | not applicable | | D8 | RED | MIO7 | High | not applicable | | D4 | Green | PL pin V18 | High | LVCMOS33 |
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512 Mbyte DDR3L SDRAM
The TE0728 SoM has two 512 GByte volatile DDR3 SDRAM IC for storing user application code and data.
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| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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B2B Name | B2B JM1 Pin | B2B JM2 Pin | B2B JM3 Pin | Direction | Notes |
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| VIN | 1,3 | - | - | Input | Supply voltage from carrier board. | | VCCO_13 | 39 | - | - | I/O |
| | VBATT | - | 1 | - | Output |
| | 3.3V | 19 | 2, 4 | 25,57 | Output | Internal 3.3V voltage level. | 1.8V | - | 5 | - | Output | Internal 1.8V voltage level. |
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | Zynq SoC bank voltages. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic Name | | Notes |
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| 500 | VCCO_MIO0_500 | 3.3V |
| | 501 | VCCO_MIO1_500 | 3.3V |
| | 502 | VCCO_DDR_502 | 1.5V |
| | 13 HR | VCCO_13 | 3.3V | Supplied by the carrier board. JM1 | | 33 HR | VCCO_33 | 3.3V | Supplied by carrier board. JM3 | | 34 HR | VCCO_34 | 3.3V |
| | 35 HR | VCCO_35 | 3.3V | Supplied by the carrier board. JM2,JM3 |
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3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)
Operating Temperature:-55°C ~ 125°C
Current Rating: 2.6A per ContactNumber of Positions: 80
Number of Rows: 2
Absolute Maximum Ratings
Processing System(PS)
| Scroll Title |
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| anchor | Table_TS_AMR_PS |
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| title | PS absolute maximum ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Symbols | Description | Min | Max | Unit |
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| VCCPINT | PS internal logic supply voltage | -0.5 | 1.1 | V | | VCCPAUX | PS auxiliary supply voltage | -0.5 | 2.0 | V | | VCCPLL | PS PLL supply | -0.5 | 2.0 | V | | VCCO_DDR | PS DDR I/O supply voltage | -0.5 | 2.0 | V | | VPREF | PS input reference voltage | -0.5 | 2.0 | V | | VCCO_MIO0 | PS MIO I/O supply voltage for HR I/O banks | -0.5 | 3.6 | V | | VCCO_MIO1 | PS MIO I/O supply voltage for HR I/O banks | 1.71 | 3.45 | V |
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Programmable Logic(PL)
| Scroll Title |
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| anchor | Table_TS_AMR_PL |
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| title | PL absolute maximum ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Symbols | Description | Min | Max | Unit |
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| VCCINT | PL internal logic supply voltage | -0.5 | 1.1 | V | | VCCPAUX | PL auxiliary supply voltage | -0.5 | 2.0 | V | | VCCPLL | PL PLL supply | -0.5 | 1.1 | V | | VPREF | PL input reference voltage | -0.5 | 2.0 | V | | VCCO | PL supply voltage for HR I/O banks | -0.5 | 3.6 | V | | VIN | I/O input voltage for HR I/O banks | 1.71 | 3.45 | V |
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| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Parameter | Min | Max | Units | Reference Document |
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| VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. | | Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. | | I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. | | Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. | | I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. | | Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. | | I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. | | Storage Temperature | -65 | 150 | °C | See Xilinx DS187 datasheet. | | CAN Transceiver Temperature | -40 | 125 | °C | See Texas Instrument sn65hvd230q-q1 datasheet. | | SPI Flash Memory | -40 | 85 | °C | See Cypress S25FL127S datasheet. | | DDR3 SDRAM Temperature | -40 | 95 | °C | See Nanya NT5CC256M16CP-DIA datasheet. |
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Physical Dimensions
| Scroll Title |
|---|
| anchor | Figure_TS_PD |
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| title | Physical dimensions drawing |
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