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Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Both Sytem System Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank pins and I²C interface. The CPLDs are connected with each other through the IO pins SC_IO0 ... SC_IO8.

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