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VG96 Connector	Count of PL IO's	Count of LVDS-pairs	SoM Control Signals and Interfaces	Notes
J8	72	24	-	-
J9	64	5	'NRST_IN', pin J9-A29	Drive to ground (Push Button S1, JB3-11 (G) on XMOD header) to reset the SoM. ²⁾
			'NRST_OUT', pin J9-B30	Incoming reset signal from SoM's watchdog (implemented on SoM's SC CPLD). ²⁾
			'BOARD_STAT', pin J9-B32	Frequently flipping signal indicating running SoM. Routed also to XMOD Header, pin JB3-9 (E).
			'BOOT_MODE1', pin J9-C31	Bootmode pin 1, use in conjunction with Bootmode pin 2.
			'BOOT_MODE2', pin J9-C32	Bootmode pin 2, use in conjunction with Bootmode pin 1.
			I²C, pins J9-A30, J9-A31	I²C1 interface of module.
			GbE SGMII, pins J9-A16, J9-A17, J9-A19 J9-A20	SGMII interface of on-module GbE PHY.

VG96 Connector	Count of IO's	Control Signals and Interfaces	Notes
J8	24 single ended	User IO	-
J8	48 single ended or 24 differential	User IO	-
J9	54 single ended	User IO	-
	10 single ended or 5 differential	User IO	-
	2	'NRST_IN',

pin J9-A29I²C-

'NRST_OUT', pins J9-A29,

J9-B30

SD IO

SoM reset signals

1

-

'BOARD_STAT', pin J9-B32

UART

-

2	'BOOT_MODE1',

pin J9-C31USB2.0-

'BOOT_MODE2' pin J9-C31,

J9-C32	-
2	I²C, pins J9-A30, J9-A31

2x 10/100

-

BaseT Ethernet

4

-GbE SGMII

GbE

MDI and

SGMII

-4JTAG

-

Table 3: General overview of PL I/O signals, SoM's interfaces and control signals connected to the VG96 connectors.

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