Page History
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| MIO | Configured as | System Controller CPLD | Notes |
|---|---|---|---|
| 0..12 | Dual QSPI | - | Dual Flash Memory on TE0808 SoM; Bootable |
| 13..23 | SD0: eMMC | - | eMMC Memory U2; Bootable |
| 24, 25 | - | CPLD (U39) MUXED | - |
| 26..29 | - | CPLD (U17 MUXED | Bootable JTAG (PJTAG0) possible |
| 30 | force reboot after FSBL-PLL config for PCIe | CPLD (U39) MUXED | - |
| 31 | PCIe reset | CPLD (U39) MUXED | - |
| 32 | - | CPLD (U39) MUXED | - |
| 33 | - | CPLD (U39) MUXED | - |
| 34..37 | - | CPLD (U39) MUXED | - |
| 38, 39 | I2C0 | - | - |
| 40 | forwarded to PWRLED_P / LED_P | CPLD (U39) MUXED | - |
| 41 | - | - | - |
| 42, 43 | UART0 | CPLD (U39) MUXED | - |
| 44 | SD_WP to FPGA | CPLD (U39) MUXED | - |
| 45..51 | SD1: SD | - | Bootable MikroSD / MMC Card |
| 52..63 | USB0 | - | - |
| 64..75 | GEM3 | - | Ethernet RGMII |
| 76, 77 | MDC / MDIO | - | Ethernet RGMII |
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| Function | MGT Lane | Required Ref Clock | Clock Source | Comment | |
|---|---|---|---|---|---|
| PCIe | PS 0 | 100 MHz | Si5345 CLK0 of prog. PLL on mounted SoM | wired on carrier board to PCIe connector J1 | |
| USB3 | PS 1 | 100 MHz | Si5345 CLK4 of prog. PLL on mounted SoM | internally on-module wired, | |
| SATA | PS 2 | 150 MHz | On-board oscillator U23 | optional: Si5345 CLK4 of prog. PLL on mounted SoM | internally on-module wired, |
| DP.0 | PS 3 | 27 MHz | Si5345 CLK5 of prog. PLL on mounted SoM | DisplayPort GT SERDES Clock Si5345 CLK6 of prog. PLL on mounted SoM |
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| Clock Source | Schematic Name | Frequency | Clock Input Destination |
|---|---|---|---|
| SiTime SiT8008BI oscillator, U10 | USB0_RCLK | 52.000000 MHz | USB 2.0 transceiver PHY U9, pin 26 |
| SiTime SiT8008BI oscillator, U13 | ETH_CLK | 25.000000 MHz | Gigabit Ethernet PHY U12, pin 34 |
| SiTime SiT8008BI oscillator, U7 | - | 25.000000 MHz | Quad PLL clock generator U35, pin 3 |
| DSC1123 oscillator, U23 | B505_CLK1 | 150.0000 MHz | PS GT Bank 505, dedicated for SATA interface |
DSC1123 oscillator, U6 optional, not equipped | B505_CLK0 | 100.0000 MHz | PS GT Bank 505, dedicated for USB /PCIe interface |
Silicon Labs 570FBB000290DG, U45 optional, not equipped | B47_L5 (LVDS) | 250.MHz | HD Bank 47 clock input |
| SiTime SiT8008BI oscillator, U25 | CLK_CPLD | 25.576000 MHz | System Controller CPLD U35, pin 128 |
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High-speed USB ULPI PHY
USB PHY (U32U9) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33U10).
| PHY Pin | ZYNQ Pin | B2B NameConnected to | Notes | ||||
|---|---|---|---|---|---|---|---|
| ULPI | MIO28 PS bank MIO52 ... MIO39-MIO63 | Zynq Ultrascale+ USB0 MIO pins are connected to the PHY. | |||||
| REFCLK | -- | 52MHz from on board oscillator (U33U9). | |||||
| REFSEL[0..2] | -- | All pins set to GND selects the external reference clock frequency (52.000000 MHz). | |||||
| RESETB | MIO7 | -SC CPLD U17 | Low active USB PHY Reset (pulled-up to PS_1.8V). | CLKOUT | MIO36 | - | Set to logic high to select reference clock (oscillator U33) operation mode. |
| DP, DM | 4- | OTG_D_P, OTG_D_N, pin J2-149 / J2-151 | port USB3.0 Hub U4 | USB data linesUSB data lines. | |||
| CPEN | - | VBUS_V_EN, pin J2-141 | External USB power switch active-high enable signal. | ||||
| VBUS | - | USB_VBUS, pin J2-145 | 5V | Connected Connect to USB VBUS via a series of resistors, see reference schematics.schematic | |||
| ID | - | ID | - | OTG_ID, pin J2-143 | For an A-device connect to the ground. For a B-device, leave floating. |
Table 811: USB PHY interface connections
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
Gigabit Ethernet PHY
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM0GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150System Controller CPLD U17, pin 70.
| PHY Pin | ZYNQ PS | B2BConnected to | Notes | |||
|---|---|---|---|---|---|---|
| MDC/MDIO | MIO52PS bank MIO76, MIO53MIO77 | - | - | PHY LEDs | - | PHY_LED0: J2-144 |
| PHY LED0..1 | SC CPLD U17, pin 67,86 | see schematic for details, forwarded to RJ45 GbE MagJack J7- | ||||
| PHY_LED2 / INTn: | - | J2-148SC CPLD U17, pin 85 | Active low interrupt line | |||
| PHY_CLK125M | - | J2-150SC CPLD U17, pin 70 | 125 MHz Ethernet PHY clock out | |||
| CONFIG | - | -SC CPLD U17, pin 65 | Permanent logic high | |||
| RESETn | MIO9 | -SC CPLD U17, pin 62 | Active low reset line | |||
| RGMII | MIO16 PS bank MIO64 ... MIO27-MIO75 | Reduced Gigabit Media Independent Interface | ||||
| SGMII- | - | Serial Gigabit Media Independent Interface | ||||
| MDI | - | PHY_MDI0: J2-120 / J2-122 PHY_MDI1: J2-126 / J2-128 PHY_MDI2: J2-132 / J2-134 PHY_MDI3: J2-138 / J2-140 | RJ45 GbE MagJack J7 | Media Dependent Interface |
Table 712: Ethernet PHY interface connections
8-Channel I²C Switches
All on-board peripherals's interfaces and on-module peripherals with exposed I²C interface to B2B connectors are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.
For this purpose, the TEBF0808 carrier board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channelsThe I2C interface on B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have PS_3.3V as reference voltage.
The I2C bus works internally on-module with reference voltage 1.8V, on the Zynq chip it is connected to the PS I2C interface via PS MIO bank 500501, pins MIO10 and MIO11MIO38 and MIO39, configured as master.
| MIO | Signal Schematic Name | Notes |
|---|---|---|
| 1038 | I2C_SCL | 1.8V reference voltage |
| 1139 | I2C_SDA | 1.8V reference voltage |
Table 913: MIO-pin assignment of the module's I2C interface
Except the RTC (U24), all I2C addresses for on-board slave devices are operating with the reference voltage PS_1.8V via voltage level translating (3.3V ↔ 1.8V) I2C bus repeater (U17).
I2C addresses for on-board devices are listed in the table below:
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Table 10: Module's I2C-interfaces overview
System Controller CPLD
The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
Quad SPI Flash Memory
On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
| Note |
|---|
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.
High-speed USB ULPI PHY
Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).
MAC Address EEPROM
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I2C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.
On-board LEDs
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LED
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listed in the table below:
| I²C Slave Devices | I2C Address | Schematic Names of I²C Bus Lines | I²C Switch |
|---|---|---|---|
| 8-channel I²C switch U16 | 0x73 | I2C_SDA / I2C_SCL | - |
| 8-channel I²C switch U27 | 0x77 | I2C_SDA / I2C_SCL | - |
| On-module Quad programmable PLL clock generator Si5345 | 0x69 | PLL_SDA / PLL_SCL | U27 |
| Configuration EEPROM U24 | 0x54 | MEM_SDA / MEM_SCL | U16 |
| Configuration EEPROM U36 | 0x52 | MEM_SDA / MEM_SCL | U16 |
| Configuration EEPROM U41 | 0x51 | MEM_SDA / MEM_SCL | U16 |
| Configuration EEPROM U22 | 0x50 | MEM_SDA / MEM_SCL | U16 |
| 8-bit I²C IO Expander U44 | 0x26 | SFP_SDA / SFP_SCL | U16 |
| 24-bit Audio Codec U3 | 0x38 | A_I2C_SDA / A_I2C_SCL | U27 |
| 4-port USB3.0 Hub configuration EEPROM U5 | 0x51 | USBH_SDA / USBH_SCL | U16 |
| 4-port USB3.0 Hub | 0x60 | USBH_SDA / USBH_SCL | U16 |
| 8-bit I²C IO Expander U38 | 0x27 | MEM_SDA / MEM_SCL | U16 |
| On-board Quad programmable PLL clock generator U35 Si5338 | 0x70 | MCLK_SDA / MCLK_SCL | U16 |
| 8-bit I²C IO Expander U34 | 0x24 | FF_E_SDA / FF_E_SCL | U27 |
| SC CPLD U17, bank 3, pins 13 (SDA), 14 (SCL) | User programmable | SC_SDA / SC_SCL | U27 |
| SC CPLD U39, bank 2, pins 52 (SDA), 50 (SCL) | User programmable | I2C_SDA / I2C_SCL | - |
Table 14: On-board peripherals' I2C-interfaces device slave addresses
There are further I²C interfaces connected to the 8-channel I²C switches U16 and U27, which are provided by connectors with I²C interface. The I²C slave addresses depend on the device, which are attached to this connectors:
| Connector | Schematic Names of I²C Bus Lines | I²C Switch |
|---|---|---|
| PCIe Connector J1 | PCIE_SDA / PCIE_SCL | U16 |
| SFP+ Connector J14A | SFP1_SDA / SFP1_SCL | U16 |
| SFP+ Connector J14B | SFP2_SDA / SFP2_SCL | U16 |
| FireFly Connector J15 | FFA_SDA / FFA_SCL | U27 |
| FireFly Connector J22 | FFB_SDA / FFB_SCL | U27 |
| FMC Connector J5 | FMC_SDA / FMC_SCL | U16 |
| PMOD Connector P1 | PMOD_SDA / PMOD_SCL | U27 |
| PMOD Connector P3 | EXT_SDA / EXT_SCL | U27 |
Table 15: On-board connectors' I2C-interfaces overview
Configuration EEPROMs
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
| EEPROM | Schematic Designator | Memory Density | Purpose |
|---|---|---|---|
| 24LC128-I/ST | U24 | 128 Kbit | user |
| 24AA025E48T-I/OT | U36 | 2 Kbit | user |
| 24AA025E48T-I/OT | U41 | 2 Kbit | user |
| 24AA025E48T-I/OT | U42 | 2 Kbit | user |
| 24LC128-I/ST | U5 | 128 Kbit | USB3.0 HUB U4 Configuration Memory |
Table 16: On-board configuration EEPROMs overview
4-port USB3.0 Hub
The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
CAN FD Transceiver
On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
eMMC Memory
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.
24-bit Audio Codec
Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).
SDIO Port Expander
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
DIP-swithches
There are two 4 bit DIP Switches on the TEBF0808, they must be used to select some options. On TEBF0808-02 default CPLD-Firmware selects boot from SD-Card, Firmware update is needed for Boot-Mode selection.
| 1 | 2 | 3 | 4 | Description |
|---|---|---|---|---|
| OFF | OFF | OFF | ON | Default |
| ON | x | x | x | PUDC = 0 |
| OFF | x | x | x | PUDC = High |
DIP Switch S5 located close to PWR push-button. This DIP Switch is connected to the two baseboard control CPLD's.
| 1 | 2 | 3 | 4 | Description |
|---|---|---|---|---|
| ON | ON | ON | ON | Default, boot from SD/eMMC, 1.8V FMC VADJ |
| ON | ON | x | x | Boot from microSD, SD or SPI Flash |
| OFF | ON | x | x | Boot from eMMC |
| ON | OFF | x | x | Boot mode PJTAG0 |
| OFF | OFF | x | x | Boot mode main JTAG |
| x | x | x | ON | FMC VADJ = 1.8V |
| x | x | x | OFF | FMC VADJ = 1.2V |
On-board LEDs
LED | Color | Connected to | Description and Notes |
|---|---|---|---|
| D1 | red | DONE signal (PS Configuration Bank 503) | This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly. |
Table 14: LED's description
| LED | Position | Description |
|---|---|---|
| D4 | Green LED near DisplayPort Connector | |
| D5 | Red LED near DisplayPort Connector | |
| D6 | Green LED near Reset Button | |
| D7 | Red LED near Reset Button |
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Power and Power-On Sequence
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Note: These pins of the DC-DC converter U8 are hard-wired to initialiy hardwired to fix the voltage to 1.8V (see schematic).
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Physical Dimensions
Module size: 52 170 mm × 76 170 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
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