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On-board Peripheral	B2B	MPSoC Unit / SoM peripheral	Description	TRM Section
FMC HPC J5, 24 LVDS pairs (48 I/O's)	J1	PL Bank (FMC_VADJ)	PL I/O-bank pins, differential pairs	FMC HPC Connector
FMC HPC J5, GTH Interface	J1	MGT Bank	10 MGT Lanes	FMC HPC Connector
SFP+ 2x1 Cage J14	J1	MGT Bank	2 MGT Lanes to dual SFP+ Connector	MGT Interfaces SFP+ and FireFly
SMA Coax J33	J1	On-module PLL	SMA Coaxial Connector to on-module PLL Clock Input pin	Programmable PLL Clock Generator
FMC HPC J5 10 LVDS pairs (20 I/O's) 1 LVDS Clock to PL Bank 2 MGT Clocks to MGT Banks	J2	PL Bank (FMC_VADJ) MGT Bank	PL I/O-bank pins, differential pairs 1 clock capable PL bank pin-pair 2 MGT clock input pin-pairs	FMC HPC Connector Programmable PLL Clock Generator
24-bit Audio Codec U3	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board 24-bit Audio Codec	Intel-PC Compatible Headers and FAN Connectors 24-bit Audio Codec
10 I/O's to SC CPLD U17	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board System Controller CPLD U17	System Controller CPDLs
8 I/O's to SC CPLD U39	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board System Controller CPLD U39	System Controller CPDLs
SDIO Interface, SD- / MMC-Card Mux	J3	PS MIO	SDIO interface connected to SD- / MMC-Card socket	MIO Bank Interfaces SDIO Port Expander
Board Peripheral's I²C Interfaces muxed to MPSoC I²C	J3	PS MIO	MPSoC I²C interface configured as master connected to on-board slaves	MIO Bank Interfaces 8-Channel I²C Switches
4 MIO to SC CPLD U17	J3	PS MIO	Functionality depending on MPSoC and CPLD firmware	System Controller CPDLs
15 MIO to SC CPLD U39	J3	PS MIO	Functionality depending on MPSoC and CPLD firmware	System Controller CPDLs
Ethernet PHY RGMII	J3	PS MIO	Ethernet PHY U12 connected per RGMII	MIO Bank Interfaces Gigabit Ethernet PHY
eMMC Flash	J3	PS MIO	eMMC Flash memory interface on PS bank	MIO Bank Interfaces eMMC Memory
USB2.0 PHY ULPI	J2	PS MIO	USB2.0 PHY U9 connected per ULPI	MIO Bank Interfaces High-speed USB ULPI PHY
SAMTEC FireFly Connector J6/J15	J2	MGT Bank	MGT Lanes to Samtec FireFly connector	MGT Interfaces SFP+ and FireFly
JTAG Interface via XMOD Header J12	J2	PS Config	MPSoC USB programmable JTAG interface	MIO Bank Interfaces JTAG Interface
USB3.0 Lane	J2	PSGT	USB3.0 PS MGT Lane	MIO Bank Interfaces PS GT Bank Interfaces
4-port USB3.0 Hub	-	-	USB3.0 (2.0 compatible) Hub with 4 ports	MIO Bank Interfaces 4-port USB3.0 Hub
USB3.0 / RJ45 GbE Connector J7, USB3.0 Connector J8	-	-	2-port USB3.0 / RJ45 GbE Connector (stacked)	MIO Bank Interfaces
25 SoM Control Signals to SC CPLDs U17 / U39	J2	On-module DC-DC converter, PLL clock generator	Control Signals, e.g. "Enable"- / "Power Good"- signals of DC-DC-converter and further on-module peripherals	Power-On Sequence Diagram Programmable PLL Clock Generator
150 MHz Osci Clock Input	J2	-	150 MHz SATA interface MGT clock	Oscillators
Signals DONE, INIT_B, SRST_B, ... to SC CPLD U39	J2	PS Config	MPSoC control signal for PS- / PL configuration	System Controller CPDLs
SATA Connector J31 PCIe Connector J1 DisplayPort J13	J2	PSGT	Connectors of the MGT based data interfaces	PS GT Bank Interfaces
PLL Clock Output to PCIe Interface On-board PLL U35 MGT Bank (B2B J3)	J2	On-module PLL clock generator	Reference clock signals of the on-module programmable PLL clock generator	Programmable PLL Clock Generator
4 I/O's to PMOD P2 via IC U33	J4	PL Bank (FMC_VADJ)	PL user I/O's accessible on PMOD connector P2	CAN FD Interface and PMOD Connectors
3 I/O's to SC CPLD U17 via IC U32	J4	PL Bank (FMC_VADJ)	PL user I/O's routed to System Controller CPLD U17	System Controller CPDLs
FMC HPC J5 46 LVDS pairs (92 I/O's) 1 LVDS Clock to PL Bank	J4	PL Bank (FMC_VADJ)	PL I/O-bank pins, differential pairs 1 clock capable PL bank pin-pair	FMC HPC Connector Programmable PLL Clock Generator

Table 1: Description of depicted on-board peripherals

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Trenz Electronic Documentation

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