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changes.mady.by.user Thorsten Trenz

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Table of contents

Table of Contents

 

 

Features

  • Mini-ITX form factor
  • ATX Power supply connector (Important 12V only Supply Required)
  • optional 12V Standard Power Plug
  • USB3 with USB3 HUB
  • Gigabit Ethernet RJ45
  • MicroSD Card (bootable)
  • eMMC (bootable)
  • PCIe slot - one PCIe lane (16 Lane Connector)
  • Displayport Single Lane
  • One SATA Connector
  • FMC HPC Slot (1.8V max VCCIO)
  • Dual SFP+
  • One Samtec FireFly (4 GT lanes bidir)
  • One Samtec FireFly connector for reverse loopback
  • Fan connectors, PC Enclosure, FMC Fan
  • Intel front panel connector (PWR/RST/LED)
  • Intel HDA Audio connector
  • CAN FD Transceiver (10 Pin IDC Connector)
  • 20 Pin ARM JTAG Connector (PS JTAG0)

PC Enclosure Rear Panel Accessible I/O

  • PCIe accepting 16 Lane PCIe cards (one lane used PS GT)
  • FMC HPC
  • Dual SFP+
  • RJ45 Gigabit Ethernet
  • 2x USB3 Host
  • Displayport (Single lane)
  • microSD
  • Two LED's
  • CAN FD (using DB9 to IDC10 Cable)
  • One PMOD

PC Front Panel I/O

  • Reset Button
  • Power Button
  • Power LED
  • HD LED
  • Intel HDA Audio
  • One USB2 HS Host port
  • One USB3 SS Host port

The above I/O interfaces are accessible using standard PC front panel cables.

Anchor
TEBF0808_REV2_loc
TEBF0808_REV2_loc

TEBF0808-REV2 Component LocationsImage Added

TEBF0808-REV2 Component Locations

CalloutFeatureComponent Designator
1PMod 2x6  SocketP2
2MicroSD Connector (Bottom)J16
3Display Port SocketJ13
4USB3.0 A 2x , RJ45 1x  StackedJ7
5Dual SFP+J14
6PCIe x16 Connector (one PCIe lane connected)J11
7FMC (1.8V max VCCIO)J5
8FAN-FMC 2 Pol.J19
9USB3 Connector 19 Pol.J8
10USB 3.0 A ConnectorJ18
11SMA (SI5338 CLK1A)J32
12SMA (B2B-IN2_P)J33
13SD Card SocketJ27
14CAN PIN-Header 6 Pol.J29
15CAN Connector 10 Pol.J24
164x Samtec B2B -Connector for TE0808J1,J2,J3,J4
17eMMC (MTFC16GJVEC-2M WT)U2
18Battery holder CR1220B1
19JTAG Connector 20 Pol.J30
20ATX Power supply connectorJ20
21PMod 2x6  SocketP3
22FFA I2C Pin HeaderJ34
23Jumper 2x4 (Configuration)S4
24BEEPER  PIN Header 4 Pol. J23
25Pin Header 12 Pol. (XMOD-FPGA Access)J12
26Pin Header 12 Pol. (XMOD-Carrier CPLD Access)J28
27Pin Header 9 Pol. (Intel front panel (PWR/RST/LED))J10
28PMod 2x6  SocketP1
29INTEL HDA Header 9 Pol.J9
30PLL I2C Connector 10 Pol.J17
31RST Push ButtonS2
32Samtec FireFly (4 GT lanes bidirectional)J6,J15
33SATA HeaderJ31
34FAN-1 4 Pol.J26
35Samtec FireFly Connector for reverse loopbackJ21,J22
36Jumper 2x4- CPLDS5
37PWR Push ButtonS1
38Power Jack 2.1mm 12VJ25

Table: Board Component Description

TE0808 GT Transceivers

GT LaneFunctionRef ClockComment
PS 0PCIe100 
PS 1USB3100 
PS 2SATA150 
PS 3DP.027 
B128 0..3FireFly  
B228 0..3FMC 0..3  
B229 0..3FMC 4..7  
B230 0.1FMC 8..9  
B230 2SFP125/156.25 
B230 3SFP125/156.25 

GT Lane Assignment

 

GT ClockFromDefaultNotes
PS 0OscillatorUsernot fitted oscillator
PS 1Oscillator150MHzSATA
PS 2Si5345100MhzUSB/PCIe
PS 3Si534527MhzDisplayPort
B128 0Si5345  
B128 1not used  
B228 0FMC GTCLK 0User 
B228 1Si5345  
B229 0FMC GTCLK 1User 
B229 1Si5345User 
B230 0Si5345User 
B230 1Si5345  

GT CLK Assignment

TE0808 MIO Assignment

 

MIODefaultAlternateNotes
0..12Dual QSPI-Bootable
13..23SD0: eMMC-Bootable
24, 25 CPLD MUXED 
26..29PJTAG0CPLD MUXEDBootable JTAG
30 CPLD MUXED 
31PCIeCPLD MUXEDSame as ZCU102
32 CPLD MUXED 
33PMUCPLD MUXEDSame as ZCU102
34..37DPauxCPLD MUXED 
38, 39I2C0- 
40, 41CAN1CPLD MUXED 
42, 43UART0CPLD MUXED 
44I2C InterruptCPLD MUXED 
45..51SD1: SD-Bootable SD Card
52..63USB0- 
64..75GEM3- 
76, 77MDIO  

MIO Assignment

TE0808 Si5345 PLL Settings

 

Input/OutputConnected toFrequencyUsed asNotes
IN0Oscillator25MHzInternal Reference 
IN2SMAUserExternal Reference 
OUT0PCIe100MHzPCIe REFCLK 
OUT1B230 CLK0125MHzFMC GT Clock 
OUT2B229 CLK1UserFMC GT Clock 
OUT3B228 CLK1UserFMC GT Clock 
OUT4B505 CLK2100MHzPCIe and USB Clock 
OUT5B505 CLK327MHzDisplayPort GT SERDES  Clock 
OUT6B128 CLK0157.6MHz (2 x 78.8)DP Video Pixel ClockSeems to be needed for DP to work
OUT7B230 CLK1156.25MhzSFP Clock 
OUT8Si5338 IN125MhzSi5338 Reference 

Recommended/Default settings for the Si5345

Note
By default Si5345 is not programmed after power on, so if FSBL is executed without proper Si5345 init or if psu_init.tcl is invoked and the design does use PS GT, then FSBL or psu_init.tcl would freeze on SERDES init code. Si5345 init does persist over reset sequence so it is possible to use known good boot files to init Si5345 and then FSBL debugging is also possible.

 

FMC Slot

FMC Slot is fitted as full FMC HPC.

Note: FMC VADJ maximum voltage is 1.8V (as HP banks do not support more than 1.8V).

SignalsMPSoC PS/PL 
FMC LAHPMapped to PL HP Banks
FMC HAHP/HDHP/HD banks mixed
CLK0PL ClockHP Bank
CLK1PL ClockHD Bank
CLK2Clock from Si5345use as clock input not supported
CLK3Clock from Si5345use as clock input not supported
GT CLK0B228 CLK1 
GT CLK1B229 CLK1 
I2CPS I2Cvia I2C multplexer
GA0, GA10Address set to 00

Optional FAN can be mounted below the FMC slot. Ther are no components below the FMC card, so FMC cards with extended component heights can be used.

 

I2C Buses

Bus #Device(s)AddressesNotes
0MUX U16  

1

Si5338 on base0x70 
2GPIO Extender0x26 
3PCIe SMBus  

4

SFP  
5SFP  
6GPIO, EEPROM0x27, 0x50, 0x51, 0x52, 0x54 
7FMC0x50 FRU EEPROMother address depend on FMC Card
8USB3 HUB For REV 2 - DO NOT SCAN will cause I2C bus freeze!
9PMOD  
10ADAU17610x38 
11FireFly  
12FireFly  
13Si53450x69Access to PLL on TE0808
14CPLD- 
15GPIO0x24 
16PMOD  

List of I2C buses and devices (bus numbers as enumerated by Linux).

Note
Do not scan bus 8, this would cause the I2C bus multiplexer to freeze until power off or hardware reset.

 

To init Si5345 use command

si534x /dev/i2c-13 0x69

 

DIP Switches

There are two 4 bit DIP Switches on the TEBF0808, they must be used to select some options. On TEBF0808-02 default CPLD-Firmware selects boot from SD-Card, Firmware update is needed for Boot-Mode selection.

 

1234Description
ONONONONDefault, boot from SD/eMMC, 1.8V FMC VADJ
ONONxxBoot from microSD, SD or SPI Flash
OFFONxxBoot from eMMC
ONOFFxxBoot mode  PJTAG0
OFFOFFxxBoot mode main  JTAG
xxxONFMC VADJ = 1.8V
xxxOFFFMC VADJ = 1.2V

DIP Switch S5 located close to PWR push-button. This DIP Switch is connected to the two baseboard control CPLD's.

 

1234Description
OFFOFFOFFONDefault
ONxxxPUDC = 0
OFFxxxPUDC = High

DIP Switch S4 located close to PCIe slot.

 

LEDs

LEDPositionDescription
D4Green LED near DisplayPort Connector 
D5Red LED near DisplayPort Connector 
D6Green LED near Reset Button 
D7Red LED near Reset Button 

 

Power

ATX Power is supported but special 12V ATX power supply must be used.

 

System controller RGPIO 

Master CPLD Read

Bit

Description
31'1' - Constant value
30'0' - Constant value
29'1' - Constant value
28'0' - Constant value
27 
26 
25 
24 
23 
22 
21SCL
20SDA
19DP PHD
18JTAG TMS
17JTAG TDI
16JTAG TCK
15JTAG SRST
14JTAG TRST
13FMC CLKDIR
12FMC TDO
11PHY LED2
10PHY LED1
9PHY LED0
8CAN Fault
7MIO29
6MIO28
5MIO27
4MIO26
3XMOD Button
2SD WP
1SW4
0SW3

Master CPLD Write

Bit

Description
31'1' - Constant value
30'0' - Constant value
29'1' - Constant value
28'0' - Constant value
27 
26 
25 
24 
23 
22 
21 
20 
19 
18 
17 
16 
15 
14 JLED2B
13 JLED2A
12 JLED1
11 SFP_LED3
10 SFP_LED2
9 SFP_LED1
8 SFP_LED0
7 LED1
6 LED0
5 USB HUB MODE1 ('1' for ROM Mode)
4 USB HUB MODE0 ('1' for ROM Mode)
3 Ethernet PHY Reset (Active High)
2 I2C Reset (Active High)
1USB HUB Reset (Active High)
0USB PHY Reset (Active High)

 

 

Slave CPLD Read

Bit

Description
31'1' - Constant value
30'0' - Constant value
29'1' - Constant value
28'0' - Constant value
27 
26 
25 
24 
23 
22 
21 
20 
19 
18 
17 
16 
15 
14 
13 
12 
11 
10 
9PLL LOL 
8XMOD Button 
7Power OK 
6Fan Senese 
5SD Detect 
4Micro SD Detect
3Power Button 
2Reset Button 
1SW2 
0SW1

Slave CPLD Write

Bit

Description
31'1' - Constant value
30'0' - Constant value
29'1' - Constant value
28'0' - Constant value
27 
26 
25 
24 
23 
22 
21 
20 
19 
18 
17 
16 
15 
14 
13 
12 
11 FAN_EN
10 HDLED_P
9 HDLED_N
8 LED_P
7 LED_N
6 LED3
5 LED2
4 FPGA PROG (Active High)
3 PCIe Reset (Active High)
2 MRESET Reset (Active High)
1SRST Reset (Active High) 
0 PLL Reset (Active High)

PCB Revisions

 

Revision 02

Known Issues:

  • signal SFP1 LOS is not connected (fixed in REV 03)

Revision 03