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Refer to https://shopwiki.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TEBF0808/REV04 for downloadabledisplay/PD/TEBF0808+TRM for the current online version of this manual and additionalother technicalavailable documentation of the product.
 

The Trenz Electronic TEBF0808 carrier board is a baseboard for the Xilinx Zynq Ultrascale+ MPSoC modules TE0808 and TE0803, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ SoMs and for developing purposes. The carrier board has a Mini-ITX form factor making it capable to be fitted into a PC enclosure. On the PC enclosure's rear and front panel, MGT interfaces and connectors are accessible, for the front panel elements there are also Intel-PC compatible headers available. 

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The MGT-banks have also clock input-pins which are exposed to the FMC connector. Following MGT-lanes are available on the FMC connectors J5:

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The FMC connector provides pins for reference clock output to the Mezzanine module and clock input to PL banks of the MPSoC:

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The FMC connector provides further interfaces like JTAG and I²C interfaces:

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FMC_TCK, pin J5-D29

FMC_TMS, pin J5-D33

FMC_TDI, pin J5-D30

FMC_TDO, pin J5- D31

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VCCIO: 3V3SB

TRST_L, pin J5-D34 pulled-up to 3V3_PER

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FMC_SCL, pin J5-C30

FMC_SDA, pin J5-C31

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I²C-lines pulled-up to 3V3_PER

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FMC_PRSNT_M2C, pin J5-H2

FMC_PG_C2M, pin J5-D1 (3V3_PER pull-up)

FMC_PG_M2C, pin J5-F1 (3V3_PER pull-up)

FMC_CLK_DIR, pin J5-B1 (pulled-down to GND)

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I²C I/O Expander U38

SC CPLD U39, bank 0

I²C I/O Expander U38

SC CPLD U17, bank 1

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'PG' = 'Power Good'-signal

'C2M' = carrier to (Mezzanine) module

'M2C' = (Mezzanine) module to carrier

Table 4: FMC connector pin-outs of available MGT lanes of the MPSoC

The FMC connector provides pins for reference clock output to the Mezzanine module and clock input to PL banks of the MPSoC:

Table 5: FMC connector pin-outs for reference clock output

The FMC connector provides further interfaces like JTAG and I²C interfaces:

Table 6: FMC connector pin-outs of available interfaces to the System Controller CPLD

Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

Table 7:  Available VCCIO voltages on FMC connector

MIO Bank Interfaces

The TEBF0808 carrier board provides several interfaces, which are configured on the MIO banks 500 .. 503 of the Zynq Ultrascale+ MPSoC.

Following table contains the assignment of the MIO pins to the configured interfaces:

Table 8:  MIO Assignment

Following interfaces are provided by the MIO bank of the Zynq Ultrascale+ MPSoC:

• 4x USB3.0 Superspeed ports (downward compatible to USB2.0 Highspeed)
• SDIO port with muxed MikroSD and MMC Card socket
• Gigabit Ethernet interface connected per RGMII
• eMMC interface
• Master I²C interface to on-board peripherals

The block-diagram below visualizes the interfaces of the MIO bank at the Zynq Ultrascale+ MPSoC and their associated on-board peripherals.

Image Added

Figure 4: TEBF0808 MIO Interfaces

PS GT Bank Interfaces

The PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:

• SATA (PS GT bank, MGT2 Lane)
• DisplayPort (PS GT bank, MGT3 Lane, only TX-pair routed)
• PCI Express (PS GT bank, MGT0 Lane)
  
  

Table 9:  PS GT Lane Assignment

Following block diagram shows the wiring of the MGT Lanes of the PS GT bank 505 to the particular high speed data interfaces:

Image Added

Figure 5: TEBF0808 PS GT Bank 505 Interface

Follwowing table contains a brief description of the control and status signals of PCIe interface:

Table 10: Description of MGT Connectors Control and Status Signals

MGT Interfaces SFP+ and FireFly

The TEBF0808 carrier board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) and Samtec "FireFly". This connectors are capable of data transmission rates up to 10 Gbit/s with SFP+ and 28 Gbit/s with FireFly.

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Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

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Table 7:  Available VCCIO voltages on FMC connector

MIO Bank Interfaces

The TEBF0808 carrier board provides several interfaces, which are configured on the MIO banks 500 .. 503 of the Zynq Ultrascale+ MPSoC.

Following table contains the assignment of the MIO pins to the configured interfaces:

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Following interfaces are provided by the MIO bank of the Zynq Ultrascale+ MPSoC:

• 4x USB3.0 Superspeed ports (downward compatible to USB2.0 Highspeed)
• SDIO port with muxed MikroSD and MMC Card socket
• Gigabit Ethernet interface connected per RGMII
• eMMC interface
• Master I²C interface to on-board peripherals

The block-diagram below visualizes the interfaces of the MIO bank at the Zynq Ultrascale+ MPSoC and their associated on-board peripherals.

Image Removed

Figure 4: TEBF0808 MIO Interfaces

PS GT Bank Interfaces

The PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:

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single lane PCIe connector

clock signal routed on carrier board to PCIe connector J1

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clock signal routed on-module,
also optional (not equipped) 100 MHz osci. U35 configurable

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optional: clock signal of SoM's prog. PLL

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DisplayPort GT SERDES clock signal,
routed on-module to MGT bank

Table 9:  PS GT Lane Assignment

Following block diagram shows the wiring of the MGT Lanes of the PS GT bank 505 to the particular high speed data interfaces:

Image Removed

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Follwowing table contains a brief description of the control and status signals of PCIe interface:

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Table 10: Description of MGT Connectors Control and Status Signals

MGT Interfaces SFP+ and FireFly

The TEBF0808 carrier board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) and Samtec "FireFly". This connectors are capable of data transmission rates up to 10 Gbit/s with SFP+ and 28 Gbit/s with FireFly.

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