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| Scroll Title |
|---|
| anchor | Table_SIP_B2B |
|---|
| title | General PL I/O to B2B connectors information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage Level | Notes |
|---|
| 13 | HR | J1 | 48 Single-end , (24 Diff) | VCCO_13 | variable from carrier | | 500 | MIO | J1 | 4 Single end | 3.3V |
| | 501 | MIO | J237 | 38 Single end | VMIO1 | variable from carrier | | 33 | HR | J3 | 34 Single end (17 Diff) | 3.3V |
| | 35 | HR | J3 J2 | 20 | 3.3V | Single end (10 Diff) 22 Single end (11 Diff) | 35 | HR | J2 | 22 | 3.3V |
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|
Ethernet PHY
Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.
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| Scroll Title |
|---|
| anchor | Table_OBP |
|---|
| title | On board peripherals |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
Quad SPI Flash Memory
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