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FPGA bank number and number of I/O signals connected to the B2B connector:
| Scroll Title |
|---|
| anchor | Table_B2B |
|---|
| title | General PL I/O to B2B connectors information. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
|---|
| 13 | JM1 | 48 | VCCO_13 |
| | 500 | JM1 | 4 | 3.3V |
| | 33 | JM3 | 34 | 3.3V |
| | 35 | JM3 | 20 | 3.3V |
| | 35 | JM2 | 22 | 3.3V |
| | 501 | JM2 | 38 | VMIO1 | MIO1 VREF is connected to resistor divider to support HSTL18 |
|
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JTAG Interface
JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
| Scroll Title |
|---|
| anchor | Table_JTG |
|---|
| title | JTAG pins Connection |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
JTAG Signal | B2B Pin |
|---|
| TMS | JM2-12 | | TDI | JM2-10 | | TDO | JM2-8 | | TCK | JM2-6 |
|
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PS7 UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
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