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title | Ethernet PHY to Zynq SoC connections |
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Bank | Signal Name | ETH1 | ETH2 | Signal Description |
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34 | ETH-RST | M15 | R16 | Ethernet reset, active-low. | 34 | ETH_COL | L16 | P20 |
| 34 | MDC | P16 | T17 | Ethernet management clock. | 34 | MDIO | M16 | T16 | Ethernet management data. | 34 | ETH_TX_D0 | J22 | N22 | Ethernet transmit data 0. Output to Ethernet PHY. | 34 | ETH_TX_D1 | M17 | P21 | Ethernet transmit data 1. Output to Ethernet PHY. | 34 | ETH_TX_D2 | K21 | P22 | Ethernet transmit data 2. Output to Ethernet PHY. | 34 | ETH_TX_D3 | M22 | R21 | Ethernet transmit data 3. Output to Ethernet PHY. | 34 | ETH_TX_EN | J21 | M21 | Ethernet transmit enable. | 34 | ETH_RX_D0 | L17 | R18 | Ethernet receive data 0. Input from Ethernet PHY. | 34 | ETH_RX_D1 | K18 | R19 | Ethernet receive data 1. Input from Ethernet PHY. | 34 | ETH_RX_D2 | J18 | T18 | Ethernet receive data 2. Input from Ethernet PHY. | 34 | ETH_RX_D3 | J20 | T19 | Ethernet receive data 3. Input from Ethernet PHY. | 34 | ETH_RX_DV | N17 | P15 | Ethernet receive data valid. |
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CAN Transceiver
Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
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Voltage Monitor Circuit
The microprocessor supervisory circuits monitor system voltages asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.
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