Page History
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- Xilinx XA7Z020-1CLG484Q (Automotive)
- Programmable Oscillator
- 2 x ARM Cortex-A9 MPCore
- 2 x 100 MBit Ethernet transceiver (PHY)
- 512 MByte DDR3L DDR3 SDRAM, 16-bit-wide
- 16 MByte QSPI Flash memory (with XiP support)
- CAN transceiver (PHY)
- 12 V power supply with watchdog
- On-board high-efficiency DC-DC converters
- System management and power sequencing
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- Three user LEDs
- Evenly-spread supply pins for good signal integrity
Initial Delivery State
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
| FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
|---|---|---|---|---|
| 13 | JM1 | 48 | VCCO_13 | |
| 500 | JM1 | 4 | 3.3V | |
| 33 | JM3 | 34 | 3.3V | |
| 35 | JM3 | 20 | 3.3V | |
| 35 | JM2 | 22 | 3.3V | |
| 501 | JM2 | 38 | VMIO1 | MIO1 VREF is connected to resistor divider to support HSTL18 |
JTAG Interface
JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
JTAG Signal | B2B Pin |
|---|---|
| TMS | JM2-12 |
| TDI | JM2-10 |
| TDO | JM2-8 |
| TCK | JM2-6 |
PS7 UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
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On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
RTC I2C
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LED
| Designator | Color | Connected to | Active Level | IO Standard |
|---|---|---|---|---|
| D9 | Green | DONE | Low | not applicable |
| D8 | RED | MIO7 | High | not applicableLVCMOS33 |
| D4 | Green | PL pin V18 | High | LVCMOS33 |
512 Mbyte DDR3L SDRAM
Ethernet
There are two 100 MBit Extreme Temperature Ethernet PHY's DP83848YB on the board. Datasheet is available from TI, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. All LED outputs have on-board pull-ups. Outputs to Magnetics have also required termination resistors on board.
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| ETH1 | ETH2 | Pullup | Notes | |
|---|---|---|---|---|
| CTREF | J3.-57 | J3.-25 | Magnetics center tap voltage | |
| TD+ | J3.-58 | J3.-28 | on-board | |
| TD- | J3.-56 | J3.-26 | on-board | |
| RD+ | J3.-52 | J3.-22 | on-board | |
| RD- | J3.-50 | J3.-20 | on-board | |
| LED1 | J3.-55 | J3.-23 | on-board | |
| LED2 | J3.-53 | J3.-21 | on-board | |
| LED3 | J3.-51 | J3.-19 | on-board | |
| POWERDOWN/INT | L21 | R20 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used. |
| RESET_N | M15 | R16 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset). |
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Technical Specifications
Absolute Maximum RatingsTechnical Specifications
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