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| Scroll Title |
|---|
| anchor | Table_OV_BP |
|---|
| title | Boot process. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
MIO pin | Signal State | Boot Mode |
|---|
MIO4 | Low | QSPI | | MIO4 | High | SD Card |
|
Zynq-7020SoC includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PS_POR_B) and the system reset signal (PS_SRST_B).
| Scroll Title |
|---|
| anchor | Table_OV_BP |
|---|
| title | Boot process. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Signal | FPGA Bank | Pin | B2B |
|---|
PS_POR_B | 500 | B5 | JM2-9 | | PS_SRST_B | 501 | C9 | JM2-2 |
|
Signals, Interfaces and Pins
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