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| MGT Bank | Type | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs from FMC Connector |
|---|---|---|---|---|
| 228 | GTH | 4 GTH lanes | B228_RX3_P, B228_RX3_N, pins J5-A10, J5-A11 B228_RX2_P, B228_RX2_N, pins J5-A6, J5-A7 B228_RX1_P, B228_RX1_N, pins J5-A2, J5-A3 B228_RX0_P, B228_RX0_N, pins J5-C6, J5-C7 | 1 reference clock signal (B228_CLK0) from FMC connector Si5345 CLK3 signal of SoM's prog. PLL on mounted SoM routed |
| 229 | GTH | 4 GTH lanes | B229_RX3_P, B229_RX3_N, pins J5-B12, J5-B13 B229_RX2_P, B229_RX2_N, pins J5-B16, J5-B17 B229_RX1_P, B229_RX1_N, pins J5-A18, J5-A19 B229_RX0_P, B229_RX0_N, pins J5-A14, J5-A15 | 1 reference clock signal (B229_CLK0) from FMC connector Si5345 CLK2 signal of SoM's prog. PLL on mounted SoM routed |
| 230 | GTH | 2 GTH lanes | B230_RX1_P, B230_RX1_N, pins J5-B4, J5-B5 B230_RX0_P, B230_RX0_N, pins J5-B8, J5-B9 | Si5345 CLK1 signal of SoM's prog. PLL on mounted SoM routed |
Table 3: FMC connector pin-outs of available MGT lanes of the MPSoC
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Following interfaces are provided by the MIO bank of the Zynq Ultrascale+ MPSoC:
- 4 4x USB3.0 Superspeed ports (downward compatible to USB2.0 Highspeed)
- SDIO port with muxed MikroSD and MMC Card socket
- Gigabit Ethernet interface connected per RGMII
- eMMC interface
- Master I²C interface to on-board peripherals
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| Function | MGT Lane | Required Ref Clock | Clock Source | Comment |
|---|---|---|---|---|
| PCIe | PS 0 | 100 MHz | Si5345 CLK0 signal of SoM's prog. PLL on mounted SoM | clock signal routed on carrier board to PCIe connector J1 |
| USB3 | PS 1 | 100 MHz | Si5345 CLK4 signal of SoM's prog. PLL on mounted SoM | clock signal routed on-module, |
| SATA | PS 2 | 150 MHz | On-board oscillator U23 | optional: Si5345 CLK4 signal of SoM's prog. PLL on mounted SoM |
| DP.0 | PS 3 | 27 MHz | Si5345 CLK5 signal of SoM's prog. PLL on mounted SoM | DisplayPort GT SERDES clock signal, Si5345 CLK6 signal of SoM's prog. PLL on mounted SoM, |
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| Function | MGT Lane | Required Ref Clock | Clock Source | Comment |
|---|---|---|---|---|
| FireFly | B128 MGT Lanes 0..3 | - | Si5345 CLK6 signal of SoM's prog. PLL on mounted SoM | clock signal on-module routed to B128 |
| SFP | B230 MGT Lane 2 | 125 / 156.25 MHz | Si5345 CLK7 signal of SoM's prog. PLL on mounted SoM | clock signal routed on carrier board to B230 |
| SFP | B230 MGT Lane 3 | 125 / 156.25 MHz | Si5345 CLK7 signal of SoM's prog. PLL on mounted SoM | clock signal routed on carrier board to B230 |
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Additionally the carrier board provides PMOD connectors with GPIO and I²C interface:
| PMOD | Interface | Connected withto | Notes |
|---|---|---|---|
| P1 | GPIO | HP Bank 65 of MPSoC (4 I/O's, B65_T0 ... B65_T3), System Controller CPLD U17 (4 I/O's, EX_IO1 ... EX_IO4) | Voltage translation via IC U33 with direction control, only singled-ended signaling possible |
| P2 | I²C | 8-channel I²C Switch U27 | Accessible on MPSoC's I²C interface through I²C switch U27 |
| P3 | I²C | 8-channel I²C Switch U27 | Accessible on MPSoC's I²C interface through I²C switch U27 |
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Following table gives an overview about the particular headers and a description about their functionalities:
| Header | Pin Name | FunctionFunctionality | Connected to | Notes |
|---|---|---|---|---|
| J10 | Pin 1, HD LED+ | HD LED Anode | SC CPLD U39 | Reset und and Power Switchswitch-pins are also connected to switch buttons S1 and S2 |
| J9 | Pin 1, PORT1L | Microphone Jack Left Microphone Jack Right Audio Out Jack Left Audio Out Jack Right Jack Detect / Mic in Ground | 24-bit Audio Codec U3 | - |
| J23 | Pin 1, 3V3SB Pin 4, S1 | 3.3V DC Supply PC compatible Beeper | SC CPLD U39 | - |
| J26 | Pin 1, GND | Ground 12V DC Supply RPM PWM | SC CPLD U39 | 4-wire PWM FAN connector |
| J35 | Pin 1, GND | Ground 12V DC Supply RPM PWM | SC CPLD U39 | 4-wire PWM FAN connector |
| J19 | Pin 1, GND | Ground 5V DC Supply | Load Switch Q3 (5V DC) | 2-wire FAN connector Fan off/on switchable by signal 'FAN_FMC_EN' on SC CPLD U39 |
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The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in of the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
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